Paparazzi UAS  v4.2.2_stable-4-gcc32f65
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spi_arch.h
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3  * Copyright (C) 2003-2005 Pascal Brisset, Antoine Drouin
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23 
27 #ifndef SPI_ARCH_H
28 #define SPI_ARCH_H
29 
30 
31 #include "mcu_periph/spi.h"
32 #include <stm32/gpio.h>
33 
34 extern void spi_arch_int_enable(void);
35 extern void spi_arch_int_disable(void);
36 
37 extern void spi_clear_rx_buf(void);
38 void spi_rw(struct spi_transaction * _trans);
39 
40 
41 /*
42 
44 // from aspirin_arch.h
45 
46 
47 extern void adxl345_write_to_reg(uint8_t addr, uint8_t val);
48 extern void adxl345_start_reading_data(void);
49 
50 */
51 
53 // from lpc spi_arch
54 
55 /*
56 
57 
58 
59 #define SpiTransmit() { \
60  while (spi_tx_idx < spi_buffer_length \
61  && bit_is_set(SSPSR, TNF)) { \
62  SpiSend(spi_buffer_output[spi_tx_idx]); \
63  spi_tx_idx++; \
64  } \
65  if (spi_tx_idx == spi_buffer_length) \
66  SpiDisableTxi(); \
67 }
68 
69 #define SpiReceive() { \
70  while (bit_is_set(SSPSR, RNE)) { \
71  if (spi_rx_idx < spi_buffer_length) { \
72  SpiRead(spi_buffer_input[spi_rx_idx]) \
73  spi_rx_idx++; \
74  } \
75  else { \
76  uint8_t foo; \
77  SpiRead(foo); \
78  } \
79  } \
80  }
81 
82 
83 
84 
85 #ifdef SPI_MASTER
86 
87 
88 // !!!!!!!!!!!!! Code for one single slave at a time !!!!!!!!!!!!!!!!!
89 #if defined SPI_SELECT_SLAVE1_PIN && defined SPI_SELECT_SLAVE0_PIN
90 #error "SPI: one single slave, please"
91 #endif
92 
93 
94 #define SpiStart() { \
95  SpiEnable(); \
96  SpiInitBuf(); \
97  SpiEnableTxi(); // enable tx fifo half empty interrupt \
98 }
99 
100 */
101 
102 /*
103  * Slave0 select : P0.20 PINSEL1 00 << 8
104  * Slave1 select : P1.20
105  *
106  */
107 
108 /*
109 
110 #define SPI_SELECT_SLAVE_IO__(port, reg) IO ## port ## reg
111 #define SPI_SELECT_SLAVE_IO_(port, reg) SPI_SELECT_SLAVE_IO__(port, reg)
112 
113 #define SPI_SELECT_SLAVE0_IODIR SPI_SELECT_SLAVE_IO_(SPI_SELECT_SLAVE0_PORT, DIR)
114 #define SPI_SELECT_SLAVE0_IOCLR SPI_SELECT_SLAVE_IO_(SPI_SELECT_SLAVE0_PORT, CLR)
115 #define SPI_SELECT_SLAVE0_IOSET SPI_SELECT_SLAVE_IO_(SPI_SELECT_SLAVE0_PORT, SET)
116 
117 #define SPI_SELECT_SLAVE1_IODIR SPI_SELECT_SLAVE_IO_(SPI_SELECT_SLAVE1_PORT, DIR)
118 #define SPI_SELECT_SLAVE1_IOCLR SPI_SELECT_SLAVE_IO_(SPI_SELECT_SLAVE1_PORT, CLR)
119 #define SPI_SELECT_SLAVE1_IOSET SPI_SELECT_SLAVE_IO_(SPI_SELECT_SLAVE1_PORT, SET)
120 
121 
122 #define SpiSelectSlave0() { \
123  spi_cur_slave = SPI_SLAVE0; \
124  SetBit(SPI_SELECT_SLAVE0_IOCLR, SPI_SELECT_SLAVE0_PIN); \
125  }
126 
127 #define SpiUnselectSlave0() { \
128  spi_cur_slave = SPI_NONE; \
129  SetBit(SPI_SELECT_SLAVE0_IOSET, SPI_SELECT_SLAVE0_PIN); \
130  }
131 
132 
133 #define SpiSelectSlave1() { \
134  spi_cur_slave = SPI_SLAVE1; \
135  SetBit(SPI_SELECT_SLAVE1_IOCLR, SPI_SELECT_SLAVE1_PIN); \
136  }
137 
138 #define SpiUnselectSlave1() { \
139  spi_cur_slave = SPI_NONE; \
140  SetBit(SPI_SELECT_SLAVE1_IOSET, SPI_SELECT_SLAVE1_PIN); \
141  }
142 
143 #ifdef SPI_SELECT_SLAVE0_PIN
144 #define SpiUnselectCurrentSlave() SpiUnselectSlave0()
145 #endif
146 
147 #ifdef SPI_SELECT_SLAVE1_PIN
148 #define SpiUnselectCurrentSlave() SpiUnselectSlave1()
149 #endif
150 
151 #endif // SPI_MASTER
152 
153 
154 #define SpiSetCPOL() (SSPCR0 |= _BV(6))
155 #define SpiClrCPOL() (SSPCR0 &= ~(_BV(6)))
156 
157 #define SpiSetCPHA() (SSPCR0 |= _BV(7))
158 #define SpiClrCPHA() (SSPCR0 &= ~(_BV(7)))
159 
160 */
161 
162 #endif // SPI_ARCH_H
void spi_arch_int_enable(void)
handling of stm32 SPI hardware
Definition: spi_arch.c:20
void spi_arch_int_disable(void)
Definition: spi_arch.c:32
arch independent SPI (Serial Peripheral Interface) API
void spi_clear_rx_buf(void)
void spi_rw(struct spi_transaction *_trans)
Definition: spi_arch.c:106