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lpcVIC.h
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1 /******************************************************************************
2  *
3  * $RCSfile$
4  * $Revision$
5  *
6  * Header file for Philips LPC ARM Processors.
7  * Copyright 2004 R O SoftWare
8  *
9  * No guarantees, warrantees, or promises, implied or otherwise.
10  * May be used for hobby or commercial purposes provided copyright
11  * notice remains intact.
12  *
13  *****************************************************************************/
14 #ifndef INC_LPC_VIC_H
15 #define INC_LPC_VIC_H
16 
17 // Vectored Interrupt Controller Registers (VIC)
18 typedef struct
19 {
20  REG32 irqStatus; // IRQ Status Register
21  REG32 fiqStatus; // FIQ Status Register
22  REG32 rawIntr; // Raw Interrupt Status Register
23  REG32 intSelect; // Interrupt Select Register
24  REG32 intEnable; // Interrupt Enable Register
25  REG32 intEnClear; // Interrupt Enable Clear Register
26  REG32 softInt; // Software Interrupt Register
27  REG32 softIntClear; // Software Interrupt Clear Register
28  REG32 protection; // Protection Enable Register
29  REG32 _pad0[3];
30  REG32 vectAddr; // Vector Address Register
31  REG32 defVectAddr; // Default Vector Address Register
32  REG32 _pad1[50];
33  REG32 vectAddr0; // Vector Address 0 Register
34  REG32 vectAddr1; // Vector Address 1 Register
35  REG32 vectAddr2; // Vector Address 2 Register
36  REG32 vectAddr3; // Vector Address 3 Register
37  REG32 vectAddr4; // Vector Address 4 Register
38  REG32 vectAddr5; // Vector Address 5 Register
39  REG32 vectAddr6; // Vector Address 6 Register
40  REG32 vectAddr7; // Vector Address 7 Register
41  REG32 vectAddr8; // Vector Address 8 Register
42  REG32 vectAddr9; // Vector Address 9 Register
43  REG32 vectAddr10; // Vector Address 10 Register
44  REG32 vectAddr11; // Vector Address 11 Register
45  REG32 vectAddr12; // Vector Address 12 Register
46  REG32 vectAddr13; // Vector Address 13 Register
47  REG32 vectAddr14; // Vector Address 14 Register
48  REG32 vectAddr15; // Vector Address 15 Register
49  REG32 _pad2[48];
50  REG32 vectCntl0; // Vector Control 0 Register
51  REG32 vectCntl1; // Vector Control 1 Register
52  REG32 vectCntl2; // Vector Control 2 Register
53  REG32 vectCntl3; // Vector Control 3 Register
54  REG32 vectCntl4; // Vector Control 4 Register
55  REG32 vectCntl5; // Vector Control 5 Register
56  REG32 vectCntl6; // Vector Control 6 Register
57  REG32 vectCntl7; // Vector Control 7 Register
58  REG32 vectCntl8; // Vector Control 8 Register
59  REG32 vectCntl9; // Vector Control 9 Register
60  REG32 vectCntl10; // Vector Control 10 Register
61  REG32 vectCntl11; // Vector Control 11 Register
62  REG32 vectCntl12; // Vector Control 12 Register
63  REG32 vectCntl13; // Vector Control 13 Register
64  REG32 vectCntl14; // Vector Control 14 Register
65  REG32 vectCntl15; // Vector Control 15 Register
66 } vicRegs_t;
67 
68 // VIC Channel Assignments
69 #define VIC_WDT 0
70 #define VIC_ARMCore0 2
71 #define VIC_ARMCore1 3
72 #define VIC_TIMER0 4
73 #define VIC_TIMER1 5
74 #define VIC_UART0 6
75 #define VIC_UART1 7
76 #define VIC_PWM 8
77 #define VIC_PWM0 8
78 #define VIC_I2C0 9
79 #define VIC_SPI 10
80 #define VIC_SPI0 10
81 #define VIC_SPI1 11
82 #define VIC_PLL 12
83 #define VIC_RTC 13
84 #define VIC_EINT0 14
85 #define VIC_EINT1 15
86 #define VIC_EINT2 16
87 #define VIC_EINT3 17
88 #define VIC_AD0 18
89 #define VIC_I2C1 19
90 #define VIC_BOD 20
91 #define VIC_AD1 21
92 #define VIC_USB 22
93 
94 #define VIC_CAN 19
95 #define VIC_CAN1_TX 20
96 #define VIC_CAN2_TX 21
97 #define VIC_CAN1_RX 26
98 #define VIC_CAN2_RX 27
99 
100 
101 // Vector Control Register bit definitions
102 #define VIC_ENABLE (1 << 5)
103 
104 // Convert Channel Number to Bit Value
105 #define VIC_BIT(chan) (1 << (chan))
106 
107 #endif
108 
#define REG32
Definition: LPC21xx.h:20
REG32 softIntClear
Definition: lpcVIC.h:27
REG32 vectAddr1
Definition: lpcVIC.h:34
REG32 vectAddr0
Definition: lpcVIC.h:33
REG32 vectCntl6
Definition: lpcVIC.h:56
REG32 vectAddr4
Definition: lpcVIC.h:37
REG32 vectAddr2
Definition: lpcVIC.h:35
REG32 vectAddr9
Definition: lpcVIC.h:42
REG32 vectAddr10
Definition: lpcVIC.h:43
REG32 softInt
Definition: lpcVIC.h:26
REG32 vectCntl4
Definition: lpcVIC.h:54
REG32 vectCntl0
Definition: lpcVIC.h:50
REG32 vectCntl1
Definition: lpcVIC.h:51
REG32 defVectAddr
Definition: lpcVIC.h:31
REG32 vectAddr11
Definition: lpcVIC.h:44
REG32 intEnable
Definition: lpcVIC.h:24
REG32 vectAddr14
Definition: lpcVIC.h:47
REG32 vectCntl5
Definition: lpcVIC.h:55
REG32 vectCntl14
Definition: lpcVIC.h:64
REG32 vectCntl11
Definition: lpcVIC.h:61
REG32 rawIntr
Definition: lpcVIC.h:22
REG32 fiqStatus
Definition: lpcVIC.h:21
REG32 vectCntl12
Definition: lpcVIC.h:62
REG32 protection
Definition: lpcVIC.h:28
REG32 intSelect
Definition: lpcVIC.h:23
REG32 vectAddr8
Definition: lpcVIC.h:41
REG32 intEnClear
Definition: lpcVIC.h:25
REG32 vectCntl8
Definition: lpcVIC.h:58
REG32 vectCntl9
Definition: lpcVIC.h:59
REG32 vectCntl2
Definition: lpcVIC.h:52
REG32 vectCntl10
Definition: lpcVIC.h:60
REG32 vectAddr5
Definition: lpcVIC.h:38
REG32 vectCntl7
Definition: lpcVIC.h:57
REG32 vectAddr12
Definition: lpcVIC.h:45
REG32 vectAddr15
Definition: lpcVIC.h:48
REG32 vectAddr3
Definition: lpcVIC.h:36
REG32 vectAddr13
Definition: lpcVIC.h:46
REG32 vectCntl3
Definition: lpcVIC.h:53
REG32 irqStatus
Definition: lpcVIC.h:20
REG32 vectAddr7
Definition: lpcVIC.h:40
REG32 vectCntl13
Definition: lpcVIC.h:63
REG32 vectCntl15
Definition: lpcVIC.h:65
REG32 vectAddr6
Definition: lpcVIC.h:39
REG32 vectAddr
Definition: lpcVIC.h:30