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max1168_arch.c
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1 /*
2  * $Id$
3  *
4  * Copyright (C) 2008-2009 Antoine Drouin <poinix@gmail.com>
5  *
6  * This file is part of paparazzi.
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8  * paparazzi is free software; you can redistribute it and/or modify
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16  * GNU General Public License for more details.
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22  */
23 
24 #include "peripherals/max1168.h"
25 
26 static void EXTINT0_ISR(void) __attribute__((naked));
27 
28 void max1168_arch_init( void ) {
29 
30  /* unselected max1168 */
32  /* SS pin is output */
34 
35  /* connect P0.16 to extint0 (EOC) */
37  /* extint0 is edge trigered */
38  SetBit(EXTMODE, MAX1168_EOC_EINT);
39  /* extint0 is trigered on falling edge */
40  ClearBit(EXTPOLAR, MAX1168_EOC_EINT);
41  /* clear pending extint0 before enabling interrupts */
42  SetBit(EXTINT, MAX1168_EOC_EINT);
43 
44  /* initialize interrupt vector */
45  VICIntSelect &= ~VIC_BIT( VIC_EINT0 ); // EXTINT0 selected as IRQ
46  VICIntEnable = VIC_BIT( VIC_EINT0 ); // EXTINT0 interrupt enabled
47  _VIC_CNTL(MAX1168_EOC_VIC_SLOT) = VIC_ENABLE | VIC_EINT0;
48  _VIC_ADDR(MAX1168_EOC_VIC_SLOT) = (uint32_t)EXTINT0_ISR; // address of the ISR
49 }
50 
51 
52 void max1168_read( void ) {
54  DEBUG_MAX_1168, MAX1168_ERR_READ_OVERUN);
55  /* select max1168 */
56  Max1168Select();
57  /* enable SPI */
58  SSP_ClearRti();
60  SSP_Enable();
61  /* write control byte - wait EOC on extint */
62  /* use internal reference and clock, sequentially scan channels 0-7 */
63  SSPDR = (1 << 0 | 1 << 3 | 7 << 5) << 8;
65 
66 }
67 
68 void EXTINT0_ISR(void) {
69  ISR_ENTRY();
71  DEBUG_MAX_1168, MAX1168_ERR_SPURIOUS_EOC);
72  /* read dummy control byte reply */
73  uint16_t foo __attribute__ ((unused));
74  foo = SSPDR;
75  /* trigger 8 frames read */
76  SSP_Send(0);
77  SSP_Send(0);
78  SSP_Send(0);
79  SSP_Send(0);
80  SSP_Send(0);
81  SSP_Send(0);
82  SSP_Send(0);
83  SSP_Send(0);
84  SSP_ClearRti();
85  SSP_EnableRti();
87  //SetBit(EXTINT, MAX1168_EOC_EINT); /* clear extint0 */
88  EXTINT = (1<<MAX1168_EOC_EINT);
89  VICVectAddr = 0x00000000; /* clear this interrupt from the VIC */
90 
91  ISR_EXIT();
92 }
#define VICIntSelect
Definition: LPC21xx.h:398
unsigned short uint16_t
Definition: types.h:16
#define MAX1168_SS_IODIR
Definition: max1168_arch.h:47
void max1168_arch_init(void)
Definition: max1168_arch.c:26
#define MAX1168_SS_PIN
Definition: max1168_arch.h:46
#define VIC_EINT0
Definition: lpcVIC.h:84
#define SSP_Send(_a)
Definition: ssp_hw.h:16
#define _VIC_CNTL(idx)
Definition: armVIC.h:19
#define MAX1168_EOC_EINT
Definition: max1168_arch.h:55
#define Max1168Unselect()
Definition: max1168_arch.h:57
#define EXTMODE
Definition: LPC21xx.h:387
#define SSP_Enable()
Definition: max11040_hw.h:44
#define SSP_DisableRti()
Definition: max11040_hw.h:53
#define STA_MAX1168_IDLE
Definition: max1168.h:33
#define _VIC_ADDR(idx)
Definition: armVIC.h:20
#define EXTPOLAR
Definition: LPC21xx.h:388
#define EXTINT
Definition: LPC21xx.h:385
#define VICVectAddr
Definition: LPC21xx.h:404
unsigned long uint32_t
Definition: types.h:18
#define MAX1168_EOC_PINSEL_BIT
Definition: max1168_arch.h:53
uint16_t foo
Definition: main_demo5.c:54
#define MAX1168_ERR_READ_OVERUN
Definition: max1168_arch.h:43
static void EXTINT0_ISR(void)
Definition: max1168_arch.c:26
#define VIC_BIT(chan)
Definition: lpcVIC.h:105
#define SSP_EnableRti()
Definition: max11040_hw.h:52
volatile uint8_t max1168_status
Definition: max1168.c:28
#define MAX1168_ERR_SPURIOUS_EOC
Definition: max1168_arch.h:44
#define SSPDR
Definition: LPC21xx.h:224
#define ISR_EXIT()
Definition: armVIC.h:61
#define SSP_ClearRti()
Definition: max11040_hw.h:54
#define MAX1168_EOC_PINSEL
Definition: max1168_arch.h:52
#define VICIntEnable
Definition: LPC21xx.h:399
#define ASSERT(x)
Definition: usb_ser_hw.c:84
#define MAX1168_EOC_PINSEL_VAL
Definition: max1168_arch.h:54
#define STA_MAX1168_READING_RES
Definition: max1168.h:35
void max1168_read(void)
Definition: max1168_arch.c:52
#define STA_MAX1168_SENDING_REQ
Definition: max1168.h:34
__attribute__((always_inline))
Definition: i2c_arch.c:35
#define Max1168Select()
Definition: max1168_arch.h:58
#define ISR_ENTRY()
Definition: armVIC.h:40
#define VIC_ENABLE
Definition: lpcVIC.h:102