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spi_arch.h File Reference
#include "std.h"
#include "LPC21xx.h"
+ Include dependency graph for spi_arch.h:

Go to the source code of this file.

Macros

#define SpiInitBuf()
 
#define SpiTransmit()
 
#define SpiReceive()
 
#define SpiEnable()
 
#define SpiDisable()
 
#define SpiEnableRti()
 
#define SpiDisableRti()
 
#define SpiClearRti()
 
#define SpiEnableTxi()
 
#define SpiDisableTxi()
 
#define SpiEnableRxi()
 
#define SpiDisableRxi()
 
#define SpiSend(a)
 
#define SpiRead(a)
 
#define SpiSetCPOL()   (SSPCR0 |= _BV(6))
 
#define SpiClrCPOL()   (SSPCR0 &= ~(_BV(6)))
 
#define SpiSetCPHA()   (SSPCR0 |= _BV(7))
 
#define SpiClrCPHA()   (SSPCR0 &= ~(_BV(7)))
 

Variables

volatile uint8_t spi_tx_idx
 handling of arm7 SPI hardware for now only SPI1 ( aka SSP ) More...
 
volatile uint8_t spi_rx_idx
 

Macro Definition Documentation

#define SpiClearRti ( )
Value:
{ \
SetBit(SSPICR, RTIC); \
}
#define SSPICR
Definition: LPC21xx.h:230
#define RTIC
Definition: LPC21xx.h:259

Definition at line 84 of file spi_arch.h.

Referenced by ADS8344_start(), max3100_transmit(), and SPI1_ISR().

#define SpiClrCPHA ( )    (SSPCR0 &= ~(_BV(7)))

Definition at line 192 of file spi_arch.h.

Referenced by baro_MS5534A_send(), and mcp355x_init().

#define SpiClrCPOL ( )    (SSPCR0 &= ~(_BV(6)))

Definition at line 189 of file spi_arch.h.

Referenced by mcp355x_init().

#define SpiDisable ( )
Value:
{ \
ClearBit(SSPCR1, SSE); \
}
#define SSPCR1
Definition: LPC21xx.h:223
#define SSE
Definition: LPC21xx.h:234

Definition at line 72 of file spi_arch.h.

Referenced by SPI1_ISR().

#define SpiDisableRti ( )
Value:
{ \
ClearBit(SSPIMSC, RTIM); \
}
#define RTIM
Definition: LPC21xx.h:240
#define SSPIMSC
Definition: LPC21xx.h:227

Definition at line 80 of file spi_arch.h.

Referenced by SPI1_ISR().

#define SpiDisableRxi ( )
Value:
{ \
ClearBit(SSPIMSC, RXIM); \
}
#define RXIM
Definition: LPC21xx.h:241
#define SSPIMSC
Definition: LPC21xx.h:227

Definition at line 100 of file spi_arch.h.

#define SpiDisableTxi ( )
Value:
{ \
ClearBit(SSPIMSC, TXIM); \
}
#define TXIM
Definition: LPC21xx.h:242
#define SSPIMSC
Definition: LPC21xx.h:227

Definition at line 92 of file spi_arch.h.

#define SpiEnable ( )
Value:
{ \
SetBit(SSPCR1, SSE); \
}
#define SSPCR1
Definition: LPC21xx.h:223
#define SSE
Definition: LPC21xx.h:234

Definition at line 68 of file spi_arch.h.

Referenced by ADS8344_start(), baro_scp_read(), baro_scp_start_high_res_measurement(), max3100_transmit(), and SPI1_ISR().

#define SpiEnableRti ( )
Value:
{ \
SetBit(SSPIMSC, RTIM); \
}
#define RTIM
Definition: LPC21xx.h:240
#define SSPIMSC
Definition: LPC21xx.h:227

Definition at line 76 of file spi_arch.h.

Referenced by ADS8344_start(), baro_scp_start_high_res_measurement(), max3100_transmit(), and SPI1_ISR().

#define SpiEnableRxi ( )
Value:
{ \
SetBit(SSPIMSC, RXIM); \
}
#define RXIM
Definition: LPC21xx.h:241
#define SSPIMSC
Definition: LPC21xx.h:227

Definition at line 96 of file spi_arch.h.

#define SpiEnableTxi ( )
Value:
{ \
SetBit(SSPIMSC, TXIM); \
}
#define TXIM
Definition: LPC21xx.h:242
#define SSPIMSC
Definition: LPC21xx.h:227

Definition at line 88 of file spi_arch.h.

#define SpiInitBuf ( )
Value:
{ \
SpiTransmit(); /* fill fifo */ \
}
bool_t spi_message_received
Definition: sim_baro.c:8
#define SpiTransmit()
Definition: spi_arch.h:45
#define FALSE
Definition: imu_chimu.h:141
volatile uint8_t spi_rx_idx
Definition: spi_arch.c:35
volatile uint8_t spi_tx_idx
handling of arm7 SPI hardware for now only SPI1 ( aka SSP )
Definition: spi_arch.c:34

Definition at line 38 of file spi_arch.h.

#define SpiRead (   a)
Value:
{ \
a = SSPDR; \
}
#define SSPDR
Definition: LPC21xx.h:224

Definition at line 108 of file spi_arch.h.

#define SpiReceive ( )
Value:
{ \
while (bit_is_set(SSPSR, RNE)) { \
} \
else { \
SpiRead(foo); \
} \
} \
}
uint8_t * spi_buffer_input
Definition: spi.c:28
#define SSPSR
Definition: LPC21xx.h:225
#define SpiRead(a)
Definition: spi_arch.h:108
uint16_t foo
Definition: main_demo5.c:54
#define RNE
Definition: LPC21xx.h:247
unsigned char uint8_t
Definition: types.h:14
volatile uint8_t spi_rx_idx
Definition: spi_arch.c:35
uint8_t spi_buffer_length
Definition: spi.c:30

Definition at line 55 of file spi_arch.h.

#define SpiSend (   a)
Value:
{ \
SSPDR = a; \
}
#define SSPDR
Definition: LPC21xx.h:224

Definition at line 104 of file spi_arch.h.

#define SpiSetCPHA ( )    (SSPCR0 |= _BV(7))

Definition at line 191 of file spi_arch.h.

Referenced by baro_MS5534A_send(), and ins_init().

#define SpiSetCPOL ( )    (SSPCR0 |= _BV(6))

Definition at line 188 of file spi_arch.h.

Referenced by ins_init().

#define SpiTransmit ( )
Value:
{ \
&& bit_is_set(SSPSR, TNF)) { \
} \
}
#define SpiSend(a)
Definition: spi_arch.h:104
uint8_t * spi_buffer_output
Definition: spi.c:29
#define SSPSR
Definition: LPC21xx.h:225
#define SpiDisableTxi()
Definition: spi_arch.h:92
#define TNF
Definition: LPC21xx.h:246
volatile uint8_t spi_tx_idx
handling of arm7 SPI hardware for now only SPI1 ( aka SSP )
Definition: spi_arch.c:34
uint8_t spi_buffer_length
Definition: spi.c:30

Definition at line 45 of file spi_arch.h.

Variable Documentation

volatile uint8_t spi_rx_idx

Definition at line 35 of file spi_arch.c.

volatile uint8_t spi_tx_idx

handling of arm7 SPI hardware for now only SPI1 ( aka SSP )

Definition at line 34 of file spi_arch.c.