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i2c_attempt2_nolib.c
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1 #include "mcu_periph/i2c.h"
2 
3 #include <stm32/rcc.h>
4 #include <stm32/gpio.h>
5 #include <stm32/flash.h>
6 #include <stm32/misc.h>
7 
8 //#include "led.h"
9 
10 //#define I2C_DEBUG_LED
11 
13 // TODO: remove this
14 
15 
16 #ifdef I2C_DEBUG_LED
17 static inline void LED1_ON(void)
18 {
19  GPIO_WriteBit(GPIOB, GPIO_Pin_6 , Bit_SET );
20 }
21 
22 static inline void LED1_OFF(void)
23 {
24  GPIO_WriteBit(GPIOB, GPIO_Pin_6 , !Bit_SET );
25 }
26 
27 static inline void LED2_ON(void)
28 {
29  GPIO_WriteBit(GPIOB, GPIO_Pin_7 , Bit_SET );
30 }
31 
32 static inline void LED2_OFF(void)
33 {
34  GPIO_WriteBit(GPIOB, GPIO_Pin_7 , !Bit_SET );
35 }
36 
37 static inline void LED_INIT(void)
38 {
39  GPIO_InitTypeDef GPIO_InitStructure;
40  RCC_APB2PeriphClockCmd( RCC_APB2Periph_GPIOB, ENABLE);
41  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_6;
42  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
43  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
44  GPIO_Init(GPIOB, &GPIO_InitStructure);
45 
46  LED1_OFF();
47  LED2_OFF();
48 }
49 
50 
51 static inline void LED_ERROR(uint8_t base, uint8_t nr)
52 {
53  LED2_ON();
54  for (int i=0;i<(base+nr);i++)
55  {
56  LED1_ON();
57  LED1_OFF();
58  }
59  LED2_OFF();
60 }
61 #endif
62 
65 
66 #ifdef USE_I2C1
67 static I2C_InitTypeDef I2C1_InitStruct = {
68  .I2C_Mode = I2C_Mode_I2C,
69  .I2C_DutyCycle = I2C_DutyCycle_2,
70  .I2C_OwnAddress1 = 0x00,
71  .I2C_Ack = I2C_Ack_Enable,
72  .I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit,
73  .I2C_ClockSpeed = 200000
74 };
75 #endif
76 
77 #ifdef USE_I2C2
78 static I2C_InitTypeDef I2C2_InitStruct = {
79  .I2C_Mode = I2C_Mode_I2C,
80  .I2C_DutyCycle = I2C_DutyCycle_2,
81  .I2C_OwnAddress1 = 0x00,
82  .I2C_Ack = I2C_Ack_Enable,
83  .I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit,
84 // .I2C_ClockSpeed = 37000
85  .I2C_ClockSpeed = 400000
86 };
87 #endif
88 
91 
92 // Bypassing the libSTM I2C functions to have more control over the reading of registers
93 // e.g. SR1 and SR2 should not always be read together as it might unwantedly clear ADDR flags etc.
94 
95 // Referring to STM32 manual:
96 // -Doc ID 13902 Rev 11
97 
98 // Status Register 1
99 
100 #define I2C_SR1_BIT_SB (1<<0) // Start Condition Met
101 #define I2C_SR1_BIT_ADDR (1<<1) // Address Sent
102 #define I2C_SR1_BIT_BTF (1<<2) // SCL held low
103 #define I2C_SR1_BIT_RXNE (1<<6) // Data Read Available
104 #define I2C_SR1_BIT_TXE (1<<7) // TX buffer space available
105 
106 #define I2C_SR1_BIT_ERR_BUS (1<<8) // Misplaced Start/Stop (usually interference)
107 #define I2C_SR1_BIT_ERR_ARLO (1<<9) // Arbitration Lost (in multimaster) or SDA short-to-ground (in single master)
108 #define I2C_SR1_BIT_ERR_AF (1<<10) // Ack Failure (too fast/too soon/no sensor/wiring break/...)
109 #define I2C_SR1_BIT_ERR_OVR (1<<11) // Overrun [data loss] (in slave) or SCL short-to-ground (in single master)
110 
111 #define I2C_SR1_BITS_ERR ((1<<8)|(1<<9)|(1<<10)|(1<<11)|(1<<12)|(1<<14)|(1<<15))
112 
113 // Status Register 2
114 
115 #define I2C_SR2_BIT_TRA (1<<2) // Transmitting
116 #define I2C_SR2_BIT_BUSY (1<<1) // Busy
117 #define I2C_SR2_BIT_MSL (1<<0) // Master Selected
118 
119 // Control Register 1
120 
121 #define I2C_CR1_BIT_PE (1<<0) // Peripheral Enable
122 #define I2C_CR1_BIT_START (1<<8) // Generate a Start
123 #define I2C_CR1_BIT_STOP (1<<9) // Generate a Stop
124 #define I2C_CR1_BIT_ACK (1<<10) // ACK / NACK
125 #define I2C_CR1_BIT_POS (1<<11) // Ack will control not the next but secondnext received byte
126 #define I2C_CR1_BIT_SWRST (1<<15) // Clear Busy Condition when no stop was detected
127 
128 // Control Register 2
129 
130 #define I2C_CR2_BIT_ITERREN (1<<8) // Error Interrupt
131 #define I2C_CR2_BIT_ITEVTEN (1<<9) // Event Interrupt
132 #define I2C_CR2_BIT_ITBUFEN (1<<10) // Buffer Interrupt
133 
134 
135 // Bit Control
136 
137 #define BIT_X_IS_SET_IN_REG(X,REG) (((REG) & (X)) == (X))
138 
141 
142 // (RE)START
143 
144 static inline void PPRZ_I2C_SEND_START(struct i2c_periph *periph)
145 {
146  I2C_TypeDef *regs = (I2C_TypeDef *) periph->reg_addr;
147 
148  periph->idx_buf = 0;
149  periph->status = I2CStartRequested;
150 
151  if (BIT_X_IS_SET_IN_REG( I2C_CR1_BIT_STOP, regs->CR1 ) )
152  {
153  regs->CR1 &= ~ I2C_CR1_BIT_STOP;
154 
155 #ifdef I2C_DEBUG_LED
156  LED2_ON();
157  LED1_ON();
158  LED1_OFF();
159  LED1_ON();
160  LED1_OFF();
161  LED1_ON();
162  LED1_OFF();
163  LED1_ON();
164  LED1_OFF();
165  LED2_OFF();
166 #endif
167  }
168  else
169  {
170 #ifdef I2C_DEBUG_LED
171  LED2_ON();
172  LED1_ON();
173  LED1_OFF();
174  LED1_ON();
175  LED1_OFF();
176  LED1_ON();
177  LED1_OFF();
178  LED2_OFF();
179 #endif
180  }
181 
182  // Issue a new start
183  regs->CR1 |= I2C_CR1_BIT_START;
184 
185  // Enable Error IRQ, Event IRQ but disable Buffer IRQ
186  regs->CR2 |= I2C_CR2_BIT_ITERREN;
187  regs->CR2 |= I2C_CR2_BIT_ITEVTEN;
188  regs->CR2 &= ~ I2C_CR2_BIT_ITBUFEN;
189 }
190 
191 // TODO: remove debug
192 #ifdef I2C_DEBUG_LED
193 
194 static inline void LED_SHOW_ACTIVE_BITS(uint16_t SR1)
195 {
196  LED1_ON();
197 
198  // Start
199  if (BIT_X_IS_SET_IN_REG( I2C_SR1_BIT_SB, SR1 ) )
200  LED2_ON();
201  else
202  LED2_OFF();
203  LED2_OFF();
204 
205  // Addr
207  LED2_ON();
208  else
209  LED2_OFF();
210  LED2_OFF();
211 
212  // BTF
214  LED2_ON();
215  else
216  LED2_OFF();
217  LED2_OFF();
218 
219  // ERROR
220  if (( SR1 & I2C_SR1_BITS_ERR ) != 0x0000)
221  LED2_ON();
222  else
223  LED2_OFF();
224  LED2_OFF();
225 
226 
227  LED1_OFF();
228 }
229 #endif
230 
233 //
234 // SUBTRANSACTION SEQUENCES
235 
240 };
241 
242 static inline enum STMI2CSubTransactionStatus stmi2c_send(I2C_TypeDef *regs, struct i2c_periph *periph, struct i2c_transaction *trans)
243 {
244  uint16_t SR1 = regs->SR1;
245 
246  // Start Condition Was Just Generated
247  if (BIT_X_IS_SET_IN_REG( I2C_SR1_BIT_SB, SR1 ) )
248  {
249  // Disable buffer interrupt
250  regs->CR2 &= ~ I2C_CR2_BIT_ITBUFEN;
251  // Send Slave address and wait for ADDR interrupt
252  regs->DR = trans->slave_addr;
253  }
254  // Address Was Sent
255  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BIT_ADDR, SR1) )
256  {
257  // Now read SR2 to clear the ADDR
258  uint16_t SR2 __attribute__ ((unused)) = regs->SR2;
259 
260  // Maybe check we are transmitting (did not loose arbitration for instance)
261  // if (! BIT_X_IS_SET_IN_REG(I2C_SR2_BIT_TRA, SR2)) { }
262 
263  // Send First max 2 bytes
264  regs->DR = trans->buf[0];
265  if (trans->len_w > 1)
266  {
267  regs->DR = trans->buf[1];
268  periph->idx_buf = 2;
269  }
270  else
271  {
272  periph->idx_buf = 1;
273  }
274 
275  // Enable buffer-space available interrupt
276  // only if there is more to send: wait for TXE, no more to send: wait for BTF
277  if ( periph->idx_buf < trans->len_w)
278  regs->CR2 |= I2C_CR2_BIT_ITBUFEN;
279  }
280  // The buffer is not full anymore AND we were not waiting for BTF
282  {
283  // Send the next byte
284  regs->DR = trans->buf[periph->idx_buf];
285  periph->idx_buf++;
286 
287  // All bytes Sent? Then wait for BTF instead
288  if ( periph->idx_buf >= trans->len_w)
289  {
290  // Not interested anymore to know the buffer has space left
291  regs->CR2 &= ~ I2C_CR2_BIT_ITBUFEN;
292  // Next interrupt will be BTF (or error)
293  }
294  }
295  // BTF: means last byte was sent
296  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BIT_BTF, SR1) )
297  {
298  if (trans->type == I2CTransTx)
299  {
300  // Tell the driver we are ready
301  trans->status = I2CTransSuccess;
302  }
303 
304  return STMI2C_SubTra_Ready;
305  }
306 
307  return STMI2C_SubTra_Busy;
308 }
309 
310 static inline enum STMI2CSubTransactionStatus stmi2c_read1(I2C_TypeDef *regs, struct i2c_transaction *trans)
311 {
312  uint16_t SR1 = regs->SR1;
313 
314  // Start Condition Was Just Generated
315  if (BIT_X_IS_SET_IN_REG( I2C_SR1_BIT_SB, SR1 ) )
316  {
317  regs->CR2 &= ~ I2C_CR2_BIT_ITBUFEN;
318  regs->DR = trans->slave_addr | 0x01;
319  }
320  // Address Was Sent
321  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BIT_ADDR, SR1) )
322  {
323  // First Clear the ACK bit: after the next byte we do not want new bytes
324  regs->CR1 &= ~ I2C_CR1_BIT_POS;
325  regs->CR1 &= ~ I2C_CR1_BIT_ACK;
326 
327  // --- next to steps MUST be executed together to avoid missing the stop
328  __disable_irq();
329 
330  // Only after setting ACK, read SR2 to clear the ADDR (next byte will start arriving)
331  uint16_t SR2 __attribute__ ((unused)) = regs->SR2;
332 
333  // Schedule a Stop
334  regs->CR1 |= I2C_CR1_BIT_STOP;
335 
336  __enable_irq();
337  // --- end of critical zone -----------
338 
339 #ifdef I2C_DEBUG_LED
340  // Program a stop
341  LED2_ON();
342  LED1_ON();
343  LED1_OFF();
344  LED2_OFF();
345 #endif
346 
347  // Enable the RXNE to get the result
348  regs->CR2 |= I2C_CR2_BIT_ITBUFEN;
349  }
350  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BIT_RXNE, SR1) )
351  {
352  regs->CR2 &= ~ I2C_CR2_BIT_ITBUFEN;
353  trans->buf[0] = regs->DR;
354 
355  // We got all the results (stop condition might still be in progress but this is the last interrupt)
356  trans->status = I2CTransSuccess;
357 
359  }
360 
361  return STMI2C_SubTra_Busy;
362 }
363 
364 static inline enum STMI2CSubTransactionStatus stmi2c_read2(I2C_TypeDef *regs, struct i2c_transaction *trans)
365 {
366  uint16_t SR1 = regs->SR1;
367 
368  // Start Condition Was Just Generated
369  if (BIT_X_IS_SET_IN_REG( I2C_SR1_BIT_SB, SR1 ) )
370  {
371  regs->CR2 &= ~ I2C_CR2_BIT_ITBUFEN;
372  regs->CR1 |= I2C_CR1_BIT_ACK;
373  regs->CR1 |= I2C_CR1_BIT_POS;
374  regs->DR = trans->slave_addr | 0x01;
375  }
376  // Address Was Sent
377  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BIT_ADDR, SR1) )
378  {
379  // BEFORE clearing ACK, read SR2 to clear the ADDR (next byte will start arriving)
380  // clearing ACK after the byte transfer has already started will NACK the next (2nd)
381  uint16_t SR2 __attribute__ ((unused)) = regs->SR2;
382 
383  // --- make absolutely sure this command is not delayed too much after the previous:
384  __disable_irq();
385  // if transfer of DR was finished already then we will get too many bytes
386  // NOT First Clear the ACK bit but only AFTER clearing ADDR
387  regs->CR1 &= ~ I2C_CR1_BIT_ACK;
388 
389  // Disable the RXNE and wait for BTF
390  regs->CR2 &= ~ I2C_CR2_BIT_ITBUFEN;
391 
392  __enable_irq();
393  // --- end of critical zone -----------
394  }
395  // Receive buffer if full, master is halted: BTF
396  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BIT_BTF, SR1) )
397  {
398  // Stop condition MUST be set BEFORE reading the DR
399  // otherwise since there is new buffer space a new byte will be read
400  regs->CR1 |= I2C_CR1_BIT_STOP;
401  // Program a stop
402 #ifdef I2C_DEBUG_LED
403  LED2_ON();
404  LED1_ON();
405  LED1_OFF();
406  LED2_OFF();
407 #endif
408 
409  trans->buf[0] = regs->DR;
410  trans->buf[1] = regs->DR;
411 
412  // We got all the results
413  trans->status = I2CTransSuccess;
414 
416  }
417 
418  return STMI2C_SubTra_Busy;
419 }
420 
421 static inline enum STMI2CSubTransactionStatus stmi2c_readmany(I2C_TypeDef *regs, struct i2c_periph *periph, struct i2c_transaction *trans)
422 {
423  uint16_t SR1 = regs->SR1;
424 
425  // Start Condition Was Just Generated
426  if (BIT_X_IS_SET_IN_REG( I2C_SR1_BIT_SB, SR1 ) )
427  {
428  regs->CR2 &= ~ I2C_CR2_BIT_ITBUFEN;
429  // The first data byte will be acked in read many so the slave knows it should send more
430  regs->CR1 &= ~ I2C_CR1_BIT_POS;
431  regs->CR1 |= I2C_CR1_BIT_ACK;
432  // Clear the SB flag
433  regs->DR = trans->slave_addr | 0x01;
434  }
435  // Address Was Sent
436  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BIT_ADDR, SR1) )
437  {
438  periph->idx_buf = 0;
439 
440  // Enable RXNE: receive an interrupt any time a byte is available
441  // only enable if MORE than 3 bytes need to be read
442  if (periph->idx_buf < (trans->len_r - 3))
443  {
444  regs->CR2 |= I2C_CR2_BIT_ITBUFEN;
445  }
446 
447  // ACK is still on to get more DATA
448  // Read SR2 to clear the ADDR (next byte will start arriving)
449  uint16_t SR2 __attribute__ ((unused)) = regs->SR2;
450  }
451  // one or more bytes are available AND we were interested in Buffer interrupts
453  {
454  // read byte until 3 bytes remain to be read (e.g. len_r = 6, -> idx=3 means idx 3,4,5 = 3 remain to be read
455  if (periph->idx_buf < (trans->len_r - 3))
456  {
457  trans->buf[periph->idx_buf] = regs->DR;
458  periph->idx_buf ++;
459  }
460  // from : 3bytes -> last byte: do nothing
461  //
462  // finally: this was the last byte
463  else if (periph->idx_buf >= (trans->len_r - 1))
464  {
465  regs->CR2 &= ~ I2C_CR2_BIT_ITBUFEN;
466 
467  // Last Value
468  trans->buf[periph->idx_buf] = regs->DR;
469  periph->idx_buf ++;
470 
471  // We got all the results
472  trans->status = I2CTransSuccess;
473 
475  }
476 
477  // Check for end of transaction: start waiting for BTF instead of RXNE
478  if (periph->idx_buf < (trans->len_r - 3))
479  {
480  regs->CR2 |= I2C_CR2_BIT_ITBUFEN;
481  }
482  else // idx >= len-3: there are 3 bytes to be read
483  {
484  // We want to halt I2C to have sufficient time to clear ACK, so:
485  // Stop listening to RXNE as it will be triggered infinitely since we did not empty the buffer
486  // on the next (second in buffer) received byte BTF will be set (buffer full and I2C halted)
487  regs->CR2 &= ~ I2C_CR2_BIT_ITBUFEN;
488  }
489  }
490  // Buffer is full while this was not a RXNE interrupt
491  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BIT_BTF, SR1) )
492  {
493  // Now the shift register and data register contain data(n-2) and data(n-1)
494  // And I2C is halted so we have time
495 
496  // --- Make absolutely sure the next 2 I2C actions are performed with no delay
497  __disable_irq();
498 
499  // First we clear the ACK while the SCL is held low by BTF
500  regs->CR1 &= ~ I2C_CR1_BIT_ACK;
501 
502  // Now that ACK is cleared we read one byte: instantly the last byte is being clocked in...
503  trans->buf[periph->idx_buf] = regs->DR;
504  periph->idx_buf ++;
505 
506  // Now the last byte is being clocked. Stop in MUST be set BEFORE the transfer of the last byte is complete
507  regs->CR1 |= I2C_CR1_BIT_STOP;
508  // Program a stop
509 #ifdef I2C_DEBUG_LED
510  LED2_ON();
511  LED1_ON();
512  LED1_OFF();
513  LED2_OFF();
514 #endif
515 
516  __enable_irq();
517  // --- end of critical zone -----------
518 
519  // read the byte2 we had in the buffer (BTF means 2 bytes available)
520  trans->buf[periph->idx_buf] = regs->DR;
521  periph->idx_buf ++;
522 
523  // Ask for an interrupt to read the last byte (which is normally still busy now)
524  // The last byte will be received with RXNE
525  regs->CR2 |= I2C_CR2_BIT_ITBUFEN;
526  }
527  else
528  {
529  // Error
530 #ifdef I2C_DEBUG_LED
531  LED2_ON();
532  LED1_ON();
533  LED2_OFF();
534  LED1_OFF();
535 #endif
536  }
537 
538  return STMI2C_SubTra_Busy;
539 }
540 
541 
542 static inline void stmi2c_clear_pending_interrupts(I2C_TypeDef *regs)
543 {
544  uint16_t SR1 = regs->SR1;
545 
546  regs->CR2 &= ~ I2C_CR2_BIT_ITBUFEN;
547 
548  // Start Condition Was Generated
549  if (BIT_X_IS_SET_IN_REG( I2C_SR1_BIT_SB, SR1 ) )
550  {
551  // SB: cleared by software when reading SR1 and writing to DR
552  regs->DR = 0x00;
553  }
554  // Address Was Sent
556  {
557  // ADDR: Cleared by software when reading SR1 and then SR2
558  uint16_t SR2 __attribute__ ((unused)) = regs->SR2;
559  }
560  // Byte Transfer Finished
562  {
563  // SB: cleared by software when reading SR1 and reading/writing to DR
564  uint8_t dummy __attribute__ ((unused)) = regs->DR;
565  regs->DR = 0x00;
566  }
567 }
568 
569 
570 static inline void i2c_error(struct i2c_periph *periph);
571 
572 static inline void i2c_event(struct i2c_periph *periph)
573 {
574 
575  /*
576  There are 7 possible reasons to get here:
577 
578  If IT_EV_FEN
579  -------------------------
580 
581  We are always interested in all IT_EV_FEV: all are required.
582 
583  1) SB // Start Condition Success in Master mode
584  2) ADDR // Address sent received Acknoledge
585  [3 ADDR10] // -- 10bit address stuff
586  [4 STOPF] // -- only for slaves: master has no stop interrupt
587  5) BTF // I2C has stopped working (it is waiting for new data, all buffers are tx_empty/rx_full)
588 
589  // Beware: using the buffered I2C has some interesting properties:
590  -in master receive mode: BTF only occurs after the 2nd received byte: after the first byte is received it is
591  in RD but the I2C can still receive a second byte. Only when the 2nd byte is received while the RxNE is 1
592  then a BTF occurs (I2C can not continue receiving bytes or they will get lost). During BTF I2C is halted (SCL held low)
593  -in master transmitmode: when writing a byte to WD, you instantly get a new TxE interrupt while the first is not
594  transmitted yet. The byte was pushed to the I2C shift register and the buffer is ready for more. You can already
595  fill new data in the buffer while the first is still being transmitted for max performance transmission.
596 
597  // Beware: besides data buffering you can/must plan several consecutive actions. You can send 2 bytes to the buffer, ask for a stop and
598  a new start in one go.
599 
600  -thanks to / because of this buffering and event sheduling there is not 1 interrupt per start / byte / stop
601  This also means you must think more in advance and a transaction could be popped from the stack even before it is
602  actually completely transmitted. But then you would not know the result yet so you have to keep it until the result
603  is known.
604 
605  // Beware: the order in which Status is read determines how flags are cleared. You should not just read SR1 & SR2 every time
606 
607  If IT_EV_FEN AND IT_EV_BUF
608  --------------------------
609 
610  Buffer event are not always wanted and are tipically switched on during longer data transfers. Make sure to turn off in time.
611 
612  6) RxNE
613  7) TxE
614 
615  --------------------------------------------------------------------------------------------------
616  // This driver uses only a subset of the pprz_i2c_states for several reasons:
617  // -we have less interrupts than the I2CStatus states (for efficiency)
618  // -STM32 has such a powerfull I2C engine with plenty of status register flags that
619  only little extra status information needs to be stored.
620 
621  // Status is re-used (abused) to remember the last COMMAND THAT WAS SENT to the STM I2C hardware.
622 
623 // TODO: check which are used
624  enum I2CStatus {
625  I2CIdle, // No more last command
626 
627  I2CStartRequested, // Last command was start
628  I2CRestartRequested, // Last command was restart
629  I2CStopRequested, // Very important to not send double stop conditions
630 
631  I2CSendingByte, // Some address/data operation
632 
633  // Following are not used
634  I2CReadingByte,
635  I2CAddrWrSent,
636  I2CAddrRdSent,
637  I2CSendingLastByte,
638  I2CReadingLastByte,
639  I2CComplete,
640  I2CFailed
641  };
642 
643  ---------
644 
645  The STM waits indefinately (holding SCL low) for user interaction:
646  a) after a master-start (waiting for address)
647  b) after an address (waiting for data)
648  not during data sending when using buffered
649  c) after the last byte is transmitted (waiting for either stop or restart)
650  not during data receiving when using buffered
651  not after the last byte is received
652 
653  -The STM I2C stalls indefinately when a stop condition was attempted that
654  did not succeed. The BUSY flag remains on.
655  -There is no STOP interrupt: use needs another way to finish.
656 
657  */
658 
659 
661  // Reading the status:
662  // - Caution: this clears several flags and can start transmissions etc...
663  // - Certain flags like STOP / (N)ACK need to be guaranteed to be set before
664  // the transmission of the byte is finished. At higher clock rates that can be
665  // quite fast: so we allow no other interrupt to be triggered in between
666  // reading the status and setting all needed flags
667 
668  // Direct Access to the I2C Registers
669  // Do not read SR2 as it might start the reading while an (n)ack bit might be needed first
670  I2C_TypeDef *regs = (I2C_TypeDef *) periph->reg_addr;
671 
672 #ifdef I2C_DEBUG_LED
673  LED1_ON();
674  LED1_OFF();
675 #endif
676 
677 
680  //
681  // TRANSACTION HANDLER
682 
683  enum STMI2CSubTransactionStatus ret = 0;
684  uint8_t restart = 0;
685 
686  // Nothing Left To Do
687  if (periph->trans_extract_idx == periph->trans_insert_idx)
688  {
689  periph->status = I2CIdle;
690  periph->errors->unexpected_event_cnt++;
691 
692  regs->CR2 &= ~ I2C_CR2_BIT_ITBUFEN; // Disable TXE, RXNE
693 #ifdef I2C_DEBUG_LED
694  LED2_ON();
695  LED1_ON();
696  LED2_OFF();
697  LED1_OFF();
698 
699  // no transaction and also an error?
700  LED_SHOW_ACTIVE_BITS(regs->SR1);
701 #endif
702 
704  i2c_error(periph);
705 
706  // There are no transactions anymore: so we are not allowed to continue
707  return;
708  }
709 
710  struct i2c_transaction* trans = periph->trans[periph->trans_extract_idx];
711 
712  if (( regs->SR1 & I2C_SR1_BITS_ERR ) != 0x0000)
713  {
714  // Set result in transaction
715  trans->status = I2CTransFailed;
716 
717  // Close the Bus
718  regs->CR2 &= ~ I2C_CR2_BIT_ITBUFEN; // Disable TXE RXNE
719 
720 #ifdef I2C_DEBUG_LED
721  LED1_ON();
722  LED2_ON();
723  LED1_OFF();
724  LED2_OFF();
725 #endif
726 
727  // Prepare for next
728  ret = STMI2C_SubTra_Ready;
729  restart = 0;
730 
732 
733  // Count it
734  i2c_error(periph);
735  }
736  else
737  {
738 
739  if (trans->type == I2CTransRx) // TxRx are converted to Rx after the Tx Part
740  {
741  switch (trans->len_r)
742  {
743  case 1:
744  ret = stmi2c_read1(regs,trans);
745  break;
746  case 2:
747  ret = stmi2c_read2(regs,trans);
748  break;
749  default:
750  ret = stmi2c_readmany(regs,periph, trans);
751  break;
752  }
753  }
754  else // TxRx or Tx
755  {
756  ret = stmi2c_send(regs,periph,trans);
757  if (trans->type == I2CTransTxRx)
758  {
759  restart = 1;
760  }
761  }
762  }
763 
764  // Sub-transaction not finished
765  if (ret == STMI2C_SubTra_Busy)
766  {
767  // Remember the last command was not start or stop
768  periph->status = I2CSendingByte;
769  }
770  else // Finished?
771  {
772  if (restart == 0)
773  {
774  if (ret == STMI2C_SubTra_Ready)
775  {
776  // Program a stop
777 #ifdef I2C_DEBUG_LED
778  LED2_ON();
779  LED1_ON();
780  LED1_OFF();
781  LED2_OFF();
782 #endif
783  // Man: p722: Stop generation after the current byte transfer or after the current Start condition is sent.
784  regs->CR1 |= I2C_CR1_BIT_STOP;
785 
786  // Silent any BTF that would occur before STOP is executed
787  regs->DR = 0x00;
788 
789  periph->status = I2CStopRequested;
790  }
791 
792  // Jump to the next transaction
793  periph->trans_extract_idx++;
795  periph->trans_extract_idx = 0;
796 
797  // if we have no more transaction to process, stop here
798  if (periph->trans_extract_idx == periph->trans_insert_idx)
799  {
800  periph->status = I2CIdle;
801 #ifdef I2C_DEBUG_LED
802  LED2_ON();
803  LED1_ON();
804  LED1_OFF();
805  LED1_ON();
806  LED1_OFF();
807  LED2_OFF();
808 #endif
809  }
810  // if not, start next transaction
811  else
812  {
813  // Restart transaction doing the Rx part now
814  periph->status = I2CStartRequested;
815  PPRZ_I2C_SEND_START(periph);
816  }
817 
818  }
819  // RxTx -> Restart and do Rx part
820  else
821  {
822  trans->type = I2CTransRx;
823  periph->status = I2CStartRequested;
824  regs->CR1 |= I2C_CR1_BIT_START;
825 
826  // Silent any BTF that would occur before SB
827  regs->DR = 0x00;
828  }
829  }
830 
831  return;
832 }
833 
834 static inline void i2c_error(struct i2c_periph *periph)
835 {
836  uint8_t err_nr = 0;
837  periph->errors->er_irq_cnt;
838  if (I2C_GetITStatus(periph->reg_addr, I2C_IT_AF)) { /* Acknowledge failure */
839  periph->errors->ack_fail_cnt++;
840  I2C_ClearITPendingBit(periph->reg_addr, I2C_IT_AF);
841  err_nr = 1;
842  }
843  if (I2C_GetITStatus(periph->reg_addr, I2C_IT_BERR)) { /* Misplaced Start or Stop condition */
844  periph->errors->miss_start_stop_cnt++;
845  I2C_ClearITPendingBit(periph->reg_addr, I2C_IT_BERR);
846  err_nr = 2;
847  }
848  if (I2C_GetITStatus(periph->reg_addr, I2C_IT_ARLO)) { /* Arbitration lost */
849  periph->errors->arb_lost_cnt++;
850  I2C_ClearITPendingBit(periph->reg_addr, I2C_IT_ARLO);
851  err_nr = 3;
852  }
853  if (I2C_GetITStatus(periph->reg_addr, I2C_IT_OVR)) { /* Overrun/Underrun */
854  periph->errors->over_under_cnt++;
855  I2C_ClearITPendingBit(periph->reg_addr, I2C_IT_OVR);
856  err_nr = 4;
857  }
858  if (I2C_GetITStatus(periph->reg_addr, I2C_IT_PECERR)) { /* PEC Error in reception */
859  periph->errors->pec_recep_cnt++;
860  I2C_ClearITPendingBit(periph->reg_addr, I2C_IT_PECERR);
861  err_nr = 5;
862  }
863  if (I2C_GetITStatus(periph->reg_addr, I2C_IT_TIMEOUT)) { /* Timeout or Tlow error */
864  periph->errors->timeout_tlow_cnt++;
865  I2C_ClearITPendingBit(periph->reg_addr, I2C_IT_TIMEOUT);
866  err_nr = 6;
867  }
868  if (I2C_GetITStatus(periph->reg_addr, I2C_IT_SMBALERT)) { /* SMBus alert */
869  periph->errors->smbus_alert_cnt++;
870  I2C_ClearITPendingBit(periph->reg_addr, I2C_IT_SMBALERT);
871  err_nr = 7;
872  }
873 
874 #ifdef I2C_DEBUG_LED
875  LED_ERROR(20, err_nr);
876 #endif
877 
878  return;
879 
880 }
881 
882 
883 /*
884  // Make sure the bus is free before resetting (p722)
885  if (regs->SR2 & (I2C_FLAG_BUSY >> 16)) {
886  // Reset the I2C block
887  I2C_SoftwareResetCmd(periph->reg_addr, ENABLE);
888  I2C_SoftwareResetCmd(periph->reg_addr, DISABLE);
889  }
890 */
891 
892 //#endif /* USE_I2C2 */
893 
894 
895 
896 
897 #ifdef USE_I2C1
898 
899 struct i2c_errors i2c1_errors;
900 
901 void i2c1_hw_init(void) {
902 
903  i2c1.reg_addr = I2C1;
904  i2c1.init_struct = &I2C1_InitStruct;
905  i2c1.scl_pin = GPIO_Pin_6;
906  i2c1.sda_pin = GPIO_Pin_7;
907  i2c1.errors = &i2c1_errors;
908 
909  /* zeros error counter */
910  ZEROS_ERR_COUNTER(i2c1_errors);
911 
912  // Extra
913 #ifdef I2C_DEBUG_LED
914  LED_INIT();
915 #endif
916 }
917 
918 void i2c1_ev_irq_handler(void) {
919  i2c_event(&i2c1);
920 }
921 
922 void i2c1_er_irq_handler(void) {
923  i2c_event(&i2c1);
924 }
925 
926 #endif /* USE_I2C1 */
927 
928 #ifdef USE_I2C2
929 
930 struct i2c_errors i2c2_errors;
931 
932 void i2c2_hw_init(void) {
933 
934  i2c2.reg_addr = I2C2;
935  i2c2.init_struct = &I2C2_InitStruct;
936  i2c2.scl_pin = GPIO_Pin_10;
937  i2c2.sda_pin = GPIO_Pin_11;
938  i2c2.errors = &i2c2_errors;
939 
940  /* zeros error counter */
941  ZEROS_ERR_COUNTER(i2c2_errors);
942 
943  /* reset peripheral to default state ( sometimes not achieved on reset :( ) */
944  //I2C_DeInit(I2C2);
945 
946  NVIC_PriorityGroupConfig(NVIC_PriorityGroup_0);
947  NVIC_InitTypeDef NVIC_InitStructure;
948 
949  /* Configure and enable I2C2 event interrupt --------------------------------*/
950  NVIC_InitStructure.NVIC_IRQChannel = I2C2_EV_IRQn;
951  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
952  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
953  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
954  NVIC_Init(&NVIC_InitStructure);
955 
956  /* Configure and enable I2C2 err interrupt ----------------------------------*/
957  NVIC_InitStructure.NVIC_IRQChannel = I2C2_ER_IRQn;
958  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
959  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
960  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
961  NVIC_Init(&NVIC_InitStructure);
962 
963  /* Enable peripheral clocks -------------------------------------------------*/
964  /* Enable I2C2 clock */
965  RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2C2, ENABLE);
966  /* Enable GPIOB clock */
967  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
968 
969  GPIO_InitTypeDef GPIO_InitStructure;
970  GPIO_InitStructure.GPIO_Pin = i2c2.scl_pin | i2c2.sda_pin;
971  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
972  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
973  GPIO_Init(GPIOB, &GPIO_InitStructure);
974 
975  I2C_DeInit(I2C2);
976 
977  // enable peripheral
978  I2C_Cmd(I2C2, ENABLE);
979 
980  I2C_Init(I2C2, i2c2.init_struct);
981 
982  // enable error interrupts
983  I2C_ITConfig(I2C2, I2C_IT_ERR, ENABLE);
984 
985 }
986 
987 
988 // TODO: this was a testing routine
989 void i2c2_setbitrate(int bitrate)
990 {
991  I2C2_InitStruct.I2C_ClockSpeed = bitrate;
992  I2C_Init(I2C2, i2c2.init_struct);
993 }
994 
995 
996 
997 void i2c2_ev_irq_handler(void) {
998  i2c_event(&i2c2);
999 }
1000 
1001 void i2c2_er_irq_handler(void) {
1002  i2c_event(&i2c2);
1003 }
1004 
1005 #endif /* USE_I2C2 */
1006 
1007 
1008 
1010 // Implement Interface Functions
1011 
1012 bool_t i2c_submit(struct i2c_periph* periph, struct i2c_transaction* t) {
1013 
1014  uint8_t temp;
1015  temp = periph->trans_insert_idx + 1;
1016  if (temp >= I2C_TRANSACTION_QUEUE_LEN) temp = 0;
1017  if (temp == periph->trans_extract_idx)
1018  return FALSE; // queue full
1019 
1020  t->status = I2CTransPending;
1021 
1022  __disable_irq();
1023  /* put transacation in queue */
1024  periph->trans[periph->trans_insert_idx] = t;
1025  periph->trans_insert_idx = temp;
1026 
1027  /* if peripheral is idle, start the transaction */
1028  // if (PPRZ_I2C_IS_IDLE(p))
1029  if (periph->status == I2CIdle)
1030  {
1031  // TODO: re-enable I2C1
1032  if (periph == &i2c1)
1033  {
1034 /*
1035  LED2_ON();
1036  LED1_ON();
1037  LED1_OFF();
1038  LED1_ON();
1039  LED1_OFF();
1040  LED1_ON();
1041  LED1_OFF();
1042  LED1_ON();
1043  LED1_OFF();
1044  LED2_OFF();
1045 */
1046  }
1047  else
1048  {
1049  PPRZ_I2C_SEND_START(periph);
1050  }
1051  }
1052  /* else it will be started by the interrupt handler when the previous transactions completes */
1053  __enable_irq();
1054 
1055  return TRUE;
1056 }
1057 
1058 bool_t i2c_idle(struct i2c_periph* periph)
1059 {
1060  return I2C_GetFlagStatus(periph->reg_addr, I2C_FLAG_BUSY) == RESET;
1061  //return periph->status == I2CIdle;
1062 }
1063 
1064 
static void LED_ERROR(uint8_t nr)
Definition: i2c_attempt1.c:46
unsigned short uint16_t
Definition: types.h:16
#define I2C_CR1_BIT_START
#define I2C_DEBUG_LED
#define I2C1
Definition: LPC21xx.h:166
static enum STMI2CSubTransactionStatus stmi2c_read1(I2C_TypeDef *regs, struct i2c_transaction *trans)
static void PPRZ_I2C_SEND_START(struct i2c_periph *periph)
void * reg_addr
Definition: i2c.h:62
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Definition: i2c.h:58
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Definition: i2c.h:71
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Definition: i2c_attempt1.c:22
#define I2C_CR1_BIT_POS
#define I2C_SR1_BITS_ERR
static void LED2_OFF(void)
Definition: i2c_attempt1.c:27
#define I2C_SR1_BIT_ADDR
volatile uint8_t idx_buf
Definition: i2c.h:61
enum I2CStatus status
Definition: i2c.h:60
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Definition: i2c.h:43
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Definition: imu_chimu.h:141
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Definition: i2c.h:77
static enum STMI2CSubTransactionStatus stmi2c_readmany(I2C_TypeDef *regs, struct i2c_periph *periph, struct i2c_transaction *trans)
volatile uint16_t timeout_tlow_cnt
Definition: i2c.h:76
Definition: i2c.h:23
#define I2C_SR1_BIT_BTF
volatile uint16_t miss_start_stop_cnt
Definition: i2c.h:72
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Definition: i2c.h:78
static enum STMI2CSubTransactionStatus stmi2c_send(I2C_TypeDef *regs, struct i2c_periph *periph, struct i2c_transaction *trans)
Definition: i2c.h:70
enum I2CTransactionStatus status
Definition: i2c.h:47
#define I2C_CR1_BIT_STOP
volatile uint16_t over_under_cnt
Definition: i2c.h:74
static void LED_SHOW_ACTIVE_BITS(I2C_TypeDef *regs)
volatile uint16_t pec_recep_cnt
Definition: i2c.h:75
#define I2C_SR1_BIT_TXE
static enum STMI2CSubTransactionStatus stmi2c_read2(I2C_TypeDef *regs, struct i2c_transaction *trans)
#define TRUE
Definition: imu_chimu.h:144
#define I2C_CR2_BIT_ITERREN
static void i2c_error(struct i2c_periph *periph)
volatile uint32_t er_irq_cnt
Definition: i2c.h:80
volatile uint8_t buf[I2C_BUF_LEN]
Definition: i2c.h:46
STMI2CSubTransactionStatus
uint8_t len_w
Definition: i2c.h:45
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Definition: i2c_attempt1.c:12
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Definition: i2c.h:44
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unsigned char uint8_t
Definition: types.h:14
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Definition: i2c.h:73
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Definition: i2c.h:57
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Definition: led_hw.h:26
#define ZEROS_ERR_COUNTER(_i2c_err)
Definition: i2c.h:94
static void i2c_event(struct i2c_periph *periph)
bool_t i2c_idle(struct i2c_periph *periph)
struct i2c_errors * errors
Definition: i2c.h:66
Definition: i2c.h:54
#define I2C_SR1_BIT_RXNE
enum I2CTransactionType type
Definition: i2c.h:42
Definition: i2c.h:10
void i2c2_setbitrate(int bitrate __attribute__((unused)))
Definition: i2c_arch.c:6
#define BIT_X_IS_SET_IN_REG(X, REG)
#define I2C_CR2_BIT_ITBUFEN
#define I2C_TRANSACTION_QUEUE_LEN
Definition: i2c.h:51
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Definition: i2c_attempt1.c:17
Definition: i2c.h:9
__attribute__((always_inline))
Definition: i2c_arch.c:35
#define I2C_SR1_BIT_SB
struct i2c_transaction * trans[I2C_TRANSACTION_QUEUE_LEN]
Definition: i2c.h:56
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#define I2C_CR2_BIT_ITEVTEN