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i2c_attempt1.c
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1 #include "mcu_periph/i2c.h"
2 
3 #include <stm32/rcc.h>
4 #include <stm32/gpio.h>
5 #include <stm32/flash.h>
6 #include <stm32/misc.h>
7 
8 //#include "led.h"
9 
11 
12 static inline void LED1_ON(void)
13 {
14  GPIO_WriteBit(GPIOB, GPIO_Pin_6 , Bit_SET );
15 }
16 
17 static inline void LED1_OFF(void)
18 {
19  GPIO_WriteBit(GPIOB, GPIO_Pin_6 , !Bit_SET );
20 }
21 
22 static inline void LED2_ON()
23 {
24  GPIO_WriteBit(GPIOB, GPIO_Pin_7 , Bit_SET );
25 }
26 
27 static inline void LED2_OFF(void)
28 {
29  GPIO_WriteBit(GPIOB, GPIO_Pin_7 , !Bit_SET );
30 }
31 
32 static inline void LED_INIT(void)
33 {
34  GPIO_InitTypeDef GPIO_InitStructure;
35  RCC_APB2PeriphClockCmd( RCC_APB2Periph_GPIOB, ENABLE);
36  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_6;
37  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
38  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
39  GPIO_Init(GPIOB, &GPIO_InitStructure);
40 
41  LED1_OFF();
42  LED2_OFF();
43 }
44 
45 
46 static inline void LED_ERROR(uint8_t nr)
47 {
48  for (int i=0;i<20;i++)
49  {
50  LED1_ON();
51  LED1_OFF();
52  if (nr == i)
53  LED2_OFF();
54  else
55  LED2_ON();
56  LED2_OFF();
57  }
58 }
59 
60 static inline void LED_STROBE2(void)
61 {
62 LED2_ON();
63 LED2_OFF();
64 LED1_ON();
65 LED1_OFF();
66 LED2_ON();
67 LED2_OFF();
68 LED1_ON();
69 LED1_OFF();
70 LED1_OFF();
71 LED1_OFF();
72 LED1_OFF();
73 
74 }
75 
77 
78 #ifdef DEBUG_I2C
79 #define SPURIOUS_INTERRUPT(_periph, _status, _event) { while(1); }
80 #define OUT_OF_SYNC_STATE_MACHINE(_periph, _status, _event) { while(1); }
81 #else
82 #define SPURIOUS_INTERRUPT(_periph, _status, _event) { }
83 #define OUT_OF_SYNC_STATE_MACHINE(_periph, _status, _event) { }
84 #endif
85 
86 #ifdef USE_I2C1
87 static I2C_InitTypeDef I2C1_InitStruct = {
88  .I2C_Mode = I2C_Mode_I2C,
89  .I2C_DutyCycle = I2C_DutyCycle_2,
90  .I2C_OwnAddress1 = 0x00,
91  .I2C_Ack = I2C_Ack_Enable,
92  .I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit,
93  .I2C_ClockSpeed = 200000
94 };
95 #endif
96 
97 #ifdef USE_I2C2
98 static I2C_InitTypeDef I2C2_InitStruct = {
99  .I2C_Mode = I2C_Mode_I2C,
100  .I2C_DutyCycle = I2C_DutyCycle_2,
101  .I2C_OwnAddress1 = 0x00,
102  .I2C_Ack = I2C_Ack_Enable,
103  .I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit,
104  .I2C_ClockSpeed = 300000
105 };
106 #endif
107 
108 
109 #ifdef USE_I2C2
110 
111 
112 
116 
117 // IDLE CHECK
118 
119 static bool_t PPRZ_I2C_IS_IDLE(struct i2c_periph* periph)
120 {
121  return I2C_GetFlagStatus(periph->reg_addr, I2C_FLAG_BUSY) == RESET;
122 }
123 
124 // (RE)START
125 
126 static inline void PPRZ_I2C_SEND_START(struct i2c_periph *periph)
127 {
128  periph->idx_buf = 0;
129  I2C_GenerateSTART(periph->reg_addr, ENABLE);
130  I2C_ITConfig(periph->reg_addr, I2C_IT_EVT | I2C_IT_ERR, ENABLE);
131  I2C_ITConfig(periph->reg_addr, I2C_IT_BUF, DISABLE);
132 }
133 
134 static void PPRZ_I2C_START_NEXT_TRANSACTION(struct i2c_periph* periph)
135 {
136  /* if we have no more transaction to process, stop here */
137  if (periph->trans_extract_idx == periph->trans_insert_idx)
138  {
139  // Should we disable just in case? normally not. So if more interrupts are
140  // triggered there is a problem and we want to know.
141  // I2C_ITConfig(periph->reg_addr, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR, DISABLE);
142  periph->status = I2CIdle;
143  }
144  /* if not, start next transaction */
145  else
146  {
147  periph->status = I2CStartRequested;
148  PPRZ_I2C_SEND_START(periph);
149  }
150 }
151 
152 static inline void PPRZ_I2C_RESTART(struct i2c_periph *periph)
153 {
154 //LED2_ON();
155 // I2C_GenerateSTOP(periph->reg_addr, ENABLE);
156 // I2C_SendData(periph->reg_addr, 0);
157 // I2C_ClearITPendingBit(periph->reg_addr, I2C_IT_BTF);
158  periph->status = I2CRestartRequested;
159  PPRZ_I2C_SEND_START(periph);
160 }
161 
162 // STOP
163 
164 static inline void PPRZ_I2C_HAS_FINISHED(struct i2c_periph *periph, struct i2c_transaction *trans, enum I2CTransactionStatus _status)
165 {
166  // Finish Current
167  trans->status = _status;
168 
169  // When finished successfully the I2C_FLAG_MLS will be cleared after the stop condition was issued.
170  // However: we do not need to wait for it to go the the next step, but if no stop condition was
171  // sent yet than we are still talking to the same slave...
172  // When we are here all paths to this function with success have already issued a STOP, the others not.
173  // Man: p722: Stop generation after the current byte transfer or after the current Start condition is sent.
174  if (_status != I2CTransSuccess)
175  {
176  // TODO: we might need to do much more here: see reset functions of antoine...
177  I2C_GenerateSTOP(periph->reg_addr, ENABLE);
178  }
179 
180  // Jump to the next
181  periph->trans_extract_idx++;
183  periph->trans_extract_idx = 0;
184 
185  PPRZ_I2C_START_NEXT_TRANSACTION(periph);
186 }
187 
190 
191 static inline void i2c_event(struct i2c_periph *periph)
192 {
193  // Referring to manual:
194  // -Doc ID 13902 Rev 11
195 
196 
197  // Check to make sure that user space has an active transaction pending
198  if (periph->trans_extract_idx == periph->trans_insert_idx)
199  {
200  // no transaction?
201  periph->errors->unexpected_event_cnt++;
202  return;
203  }
204 
205  struct i2c_transaction* trans = periph->trans[periph->trans_extract_idx];
206 
207  /*
208  There are 7 possible reasons to get here:
209 
210  If IT_EV_FEN
211  -------------------------
212 
213  We are always interested in all IT_EV_FEV: all are required.
214 
215  1) SB // Start Condition Success in Master mode
216  2) ADDR // Address sent received Acknoledge
217  [3 ADDR10] // -- 10bit address stuff
218  [4 STOPF] // -- only for slaves: master has no stop interrupt
219  5) BTF // I2C has stopped working (it is waiting for new data, all buffers are tx_empty/rx_full)
220 
221  // Beware: using the buffered I2C has some interesting properties:
222  -when receiving BTF only occurs after the 2nd received byte: after the first byte is received it is
223  in RD but the I2C can still receive a second byte. Only when the 2nd byte is received while the RxNE is 1
224  then a BTF occurs (I2C can not continue receiving bytes or they will get lost)
225  -when transmitting, and writing a byte to WD, you instantly get a new TxE interrupt while the first is not
226  transmitted yet. The byte was pushed to the I2C serializer and the buffer is ready for more. You can already
227  fill new data in the buffer while the first is still being transmitted for max performance transmission.
228 
229  // Beware: the order in which Status is read determines how flags are cleared.
230 
231  If IT_EV_FEN AND IT_EV_BUF
232  --------------------------
233 
234  We are always interested in buffer interrupts IT_EV_BUF except in transmission when all data was sent
235 
236  6) RxNE
237  7) TxE
238 
239  --------------------------------------------------------------------------------------------------
240  // This driver uses only a subset of the pprz_i2c_states for several reasons:
241  // -we have less interrupts than the I2CStatus states (for efficiency)
242  // -status register flags better correspond to reality, especially in case of I2C errors
243 
244  enum I2CStatus {
245  I2CIdle, // Dummy: Actual I2C Peripheral idle detection is safer with the
246  // hardware status register flag I2C_FLAG_BUSY.
247 
248  I2CStartRequested, // EV5: used to differentiate S en Sr
249  I2CRestartRequested, // EV5: used to differentiate S en Sr
250 
251  I2CSendingByte, // Not used: using the hardware status reg I2C_FLAG_TRA
252  I2CReadingByte,
253  I2CAddrWrSent, // Since we can do many things at once and we
254  I2CAddrRdSent, // have buffered sending, these states
255  I2CSendingLastByte, // do not correspond to the real state of the
256  I2CReadingLastByte, // STM I2C driver so they are not used
257  I2CStopRequested,
258 
259  I2CComplete, // Used to provide the result
260  I2CFailed
261  };
262 
263  ---------
264 
265  The STM waits (holding SCL low) for user interaction:
266  a) after a master-start (waiting for address)
267  b) after an address (waiting for data)
268  not during data sending when using buffered
269  c) after the last byte is transmitted (waiting for either stop or restart)
270  not during data receiving when using buffered
271  not after the last byte is received
272 
273  */
274 
275 
277  // Reading the status:
278  // - Caution: this clears several flags and can start transmissions etc...
279  // - Certain flags like STOP / (N)ACK need to be guaranteed to be set before
280  // the transmission of the byte is finished. At higher clock rates that can be
281  // quite fast: so we allow no other interrupt to be triggered in between
282  // reading the status and setting all needed flags
283 
284 
285  LED1_ON();
286 
287  //I2C_TypeDef *regs = (I2C_TypeDef *) periph->reg_addr;
288 
289  //__disable_irq();
290  uint32_t event = I2C_GetLastEvent(periph->reg_addr);
291 
292  //uint32_t event = (((uint32_t)(regs->SR2)) << 16) + regs->SR1;
293 
294  if (event & I2C_FLAG_TXE)
295  {
296  LED2_ON();
297  }
298 
299 
302  // START: Start Condition in Master Mode:
303  // STM Manual Ev5
304  if (event & I2C_FLAG_SB)
305  {
306  // Periph was waiting for Start
307  if (periph->status == I2CStartRequested)
308  {
309  // Send Read Slave Address
310  if(trans->type == I2CTransRx)
311  {
312  I2C_Send7bitAddress(periph->reg_addr, trans->slave_addr, I2C_Direction_Receiver);
313  }
314  // Send Write Slave Address
315  else
316  {
317  I2C_Send7bitAddress(periph->reg_addr, trans->slave_addr, I2C_Direction_Transmitter);
318  }
319  I2C_ITConfig(periph->reg_addr, I2C_IT_BUF, ENABLE);
320  }
321  // Waiting for Restart: Always Rx
322  else if (periph->status == I2CRestartRequested)
323  {
324  I2C_Send7bitAddress(periph->reg_addr, trans->slave_addr, I2C_Direction_Receiver);
325  I2C_ITConfig(periph->reg_addr, I2C_IT_BUF, ENABLE);
326  }
327  // Problem: this problem need to be triggerd as if the
328  // status was not OK then the buf size is also bad
329  else
330  {
331  PPRZ_I2C_HAS_FINISHED(periph, trans, I2CTransFailed);
332  }
333  periph->status = I2CAddrWrSent;
334  }
335 
338  // TRANSMIT: Buffer Can accept the next byte for transmission
339  // --> this means we HAVE TO fill the buffer and/or disable buf interrupts (otherwise this interrupt
340  // will be triggered until a start/stop occurs which can be quite long = many spurrious interrupts)
341  // STM Manual Ev8
342  else if (event & I2C_FLAG_TXE) // only possible when TRA(nsmitter) and no flag tra/start/stop/addr
343  {
344  if (periph->status == I2CRestartRequested)
345  {
346  // Neglect this interrupt: We just issued the restart last session already
347  PPRZ_I2C_RESTART(periph);
348  }
349 
350  // Do we have more data? and there is buffer room?
351  // (neglect BTF: if it was set it just means we were too slow)
352  else if (periph->idx_buf < trans->len_w)
353  {
354  I2C_SendData(periph->reg_addr, trans->buf[periph->idx_buf]);
355  periph->idx_buf++;
356  // Was this one the Last? -> Disable the buf interrupt (until next start) and wait for BTF
357  // -we could gain a bit of efficiency by already starting the next action but for
358  // code-readability we will wait until the last tx-byte is sent
359  if (periph->idx_buf >= trans->len_w)
360  {
361  I2C_ITConfig(periph->reg_addr, I2C_IT_BUF, DISABLE);
362  // If this is followed by a restart: then we need to set the startbit to avoid extra interrupts.
363  if (trans->type != I2CTransTx)
364  {
365  I2C_GenerateSTOP(periph->reg_addr, ENABLE);
366  }
367  }
368  }
369 
370  else if (event & I2C_FLAG_BTF)
371  {
372  // Ready -> Stop
373  if (trans->type == I2CTransTx)
374  {
375  // STM Manual Ev8_2
376  I2C_GenerateSTOP(periph->reg_addr, ENABLE);
377  PPRZ_I2C_HAS_FINISHED(periph, trans, I2CTransSuccess);
378  }
379  // Rx/Trans -> Restart:
380  // Do not wait for BTF
381  }
382  // If we had no more data but got no BTF then there is a problem
383  else
384  {
385  PPRZ_I2C_HAS_FINISHED(periph, trans, I2CTransFailed);
386  }
387  }
388 
391  // RECEIVE:
392  // while receiving: the master needs to signal to the slave if more data is needed
393  else if ((event & I2C_FLAG_ADDR) || (event & I2C_FLAG_RXNE))
394  {
395  // data is available every time RXNE is set. If BTF is set it means that 2 bytes are
396  // ready to read (one in shift register) and I2C has stopped until the buffer can accept new data.
397  if (event & I2C_FLAG_RXNE)
398  {
399  uint8_t read_byte = I2C_ReceiveData(periph->reg_addr);
400  if (periph->idx_buf < trans->len_r)
401  {
402  trans->buf[periph->idx_buf] = read_byte;
403  periph->idx_buf++;
404  }
405  }
406 
407  // This last byte has arrived
408  if (periph->idx_buf >= trans->len_r)
409  {
410  PPRZ_I2C_HAS_FINISHED(periph, trans, I2CTransSuccess);
411  }
412  // Tell the Slave it will be the last one
413  else if (periph->idx_buf >= trans->len_r-1)
414  {
415  I2C_AcknowledgeConfig(periph->reg_addr, DISABLE); // give them a nack once it's done
416  I2C_GenerateSTOP(periph->reg_addr, ENABLE); // and follow with a stop
417  }
418  // Ask the Slave to send more
419  else
420  {
421  I2C_AcknowledgeConfig(periph->reg_addr, ENABLE);
422  }
423 
424  }
425 
426  // Now re-enable IRQ... it's been too long
427  // __enable_irq();
428 
429 
430 
431  LED2_OFF();
432  LED1_OFF();
433 
434 
435 }
436 
437 static inline void i2c_error(struct i2c_periph *periph)
438 {
439  uint8_t err_nr = 0;
440  periph->errors->er_irq_cnt;
441  if (I2C_GetITStatus(periph->reg_addr, I2C_IT_AF)) { /* Acknowledge failure */
442  periph->errors->ack_fail_cnt++;
443  I2C_ClearITPendingBit(periph->reg_addr, I2C_IT_AF);
444  err_nr = 1;
445  }
446  if (I2C_GetITStatus(periph->reg_addr, I2C_IT_BERR)) { /* Misplaced Start or Stop condition */
447  periph->errors->miss_start_stop_cnt++;
448  I2C_ClearITPendingBit(periph->reg_addr, I2C_IT_BERR);
449  err_nr = 2;
450  }
451  if (I2C_GetITStatus(periph->reg_addr, I2C_IT_ARLO)) { /* Arbitration lost */
452  periph->errors->arb_lost_cnt++;
453  I2C_ClearITPendingBit(periph->reg_addr, I2C_IT_ARLO);
454  // I2C_AcknowledgeConfig(I2C2, DISABLE);
455  // uint8_t dummy __attribute__ ((unused)) = I2C_ReceiveData(I2C2);
456  // I2C_GenerateSTOP(I2C2, ENABLE);
457  err_nr = 3;
458  }
459  if (I2C_GetITStatus(periph->reg_addr, I2C_IT_OVR)) { /* Overrun/Underrun */
460  periph->errors->over_under_cnt++;
461  I2C_ClearITPendingBit(periph->reg_addr, I2C_IT_OVR);
462  err_nr = 4;
463  }
464  if (I2C_GetITStatus(periph->reg_addr, I2C_IT_PECERR)) { /* PEC Error in reception */
465  periph->errors->pec_recep_cnt++;
466  I2C_ClearITPendingBit(periph->reg_addr, I2C_IT_PECERR);
467  err_nr = 5;
468  }
469  if (I2C_GetITStatus(periph->reg_addr, I2C_IT_TIMEOUT)) { /* Timeout or Tlow error */
470  periph->errors->timeout_tlow_cnt++;
471  I2C_ClearITPendingBit(periph->reg_addr, I2C_IT_TIMEOUT);
472  err_nr = 6;
473  }
474  if (I2C_GetITStatus(periph->reg_addr, I2C_IT_SMBALERT)) { /* SMBus alert */
475  periph->errors->smbus_alert_cnt++;
476  I2C_ClearITPendingBit(periph->reg_addr, I2C_IT_SMBALERT);
477  err_nr = 7;
478  }
479 
480 
481  LED_ERROR(err_nr);
482 
483 
484  // Check to make sure that user space has an active transaction pending
485  if (periph->trans_extract_idx == periph->trans_insert_idx)
486  {
487  // no transaction?
488  periph->errors->unexpected_event_cnt++;
489  err_nr = 8;
490  return;
491  }
492 
493  struct i2c_transaction* trans = periph->trans[periph->trans_extract_idx];
494  //abort_and_reset(p);
495 
496 
497 
498  PPRZ_I2C_HAS_FINISHED(periph, trans, I2CTransFailed);
499 
500 
501 }
502 
503 
504 /*
505  // Make sure the bus is free before resetting (p722)
506  if (regs->SR2 & (I2C_FLAG_BUSY >> 16)) {
507  // Reset the I2C block
508  I2C_SoftwareResetCmd(periph->reg_addr, ENABLE);
509  I2C_SoftwareResetCmd(periph->reg_addr, DISABLE);
510  }
511 */
512 
513 #endif /* USE_I2C2 */
514 
515 
516 
517 
518 #ifdef USE_I2C1
519 
520 struct i2c_errors i2c1_errors;
521 
522 void i2c1_hw_init(void) {
523 
524  i2c1.reg_addr = I2C1;
525  i2c1.init_struct = &I2C1_InitStruct;
526  i2c1.scl_pin = GPIO_Pin_6;
527  i2c1.sda_pin = GPIO_Pin_7;
528  i2c1.errors = &i2c1_errors;
529 
530  /* zeros error counter */
531  ZEROS_ERR_COUNTER(i2c1_errors);
532 
533  // Extra
534  LED_INIT();
535 }
536 
537 void i2c1_ev_irq_handler(void) {
538  i2c_event(&i2c1);
539 }
540 
541 void i2c1_er_irq_handler(void) {
542  i2c_error(&i2c1);
543 }
544 
545 #endif /* USE_I2C1 */
546 
547 #ifdef USE_I2C2
548 
549 struct i2c_errors i2c2_errors;
550 
551 void i2c2_hw_init(void) {
552 
553  i2c2.reg_addr = I2C2;
554  i2c2.init_struct = &I2C2_InitStruct;
555  i2c2.scl_pin = GPIO_Pin_10;
556  i2c2.sda_pin = GPIO_Pin_11;
557  i2c2.errors = &i2c2_errors;
558 
559  /* zeros error counter */
560  ZEROS_ERR_COUNTER(i2c2_errors);
561 
562  /* reset peripheral to default state ( sometimes not achieved on reset :( ) */
563  //I2C_DeInit(I2C2);
564 
565  NVIC_PriorityGroupConfig(NVIC_PriorityGroup_0);
566  NVIC_InitTypeDef NVIC_InitStructure;
567 
568  /* Configure and enable I2C2 event interrupt --------------------------------*/
569  NVIC_InitStructure.NVIC_IRQChannel = I2C2_EV_IRQn;
570  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
571  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
572  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
573  NVIC_Init(&NVIC_InitStructure);
574 
575  /* Configure and enable I2C2 err interrupt ----------------------------------*/
576  NVIC_InitStructure.NVIC_IRQChannel = I2C2_ER_IRQn;
577  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
578  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
579  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
580  NVIC_Init(&NVIC_InitStructure);
581 
582  /* Enable peripheral clocks -------------------------------------------------*/
583  /* Enable I2C2 clock */
584  RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2C2, ENABLE);
585  /* Enable GPIOB clock */
586  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
587 
588  GPIO_InitTypeDef GPIO_InitStructure;
589  GPIO_InitStructure.GPIO_Pin = i2c2.scl_pin | i2c2.sda_pin;
590  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
591  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
592  GPIO_Init(GPIOB, &GPIO_InitStructure);
593 
594  I2C_DeInit(I2C2);
595 
596  // enable peripheral
597  I2C_Cmd(I2C2, ENABLE);
598 
599  I2C_Init(I2C2, i2c2.init_struct);
600 
601 // I2C_SoftwareResetCmd(I2C2, ENABLE);
602 // I2C_SoftwareResetCmd(I2C2, DISABLE);
603 
604  // Reset and initialize I2C HW
605  // enable error interrupts
606  I2C_ITConfig(I2C2, I2C_IT_ERR, ENABLE);
607 
608 // i2c_reset_init(&i2c2);
609 
610 }
611 
612 
613 void i2c2_ev_irq_handler(void) {
614  i2c_event(&i2c2);
615 }
616 
617 void i2c2_er_irq_handler(void) {
618  i2c_error(&i2c2);
619 }
620 
621 #endif /* USE_I2C2 */
622 
623 
624 
626 // Implement Interface Functions
627 
628 bool_t i2c_submit(struct i2c_periph* periph, struct i2c_transaction* t) {
629 
630  uint8_t temp;
631  temp = periph->trans_insert_idx + 1;
632  if (temp >= I2C_TRANSACTION_QUEUE_LEN) temp = 0;
633  if (temp == periph->trans_extract_idx)
634  return FALSE; // queue full
635 
636  t->status = I2CTransPending;
637 
638  __disable_irq();
639  /* put transacation in queue */
640  periph->trans[periph->trans_insert_idx] = t;
641  periph->trans_insert_idx = temp;
642 
643  /* if peripheral is idle, start the transaction */
644  // if (PPRZ_I2C_IS_IDLE(p))
645  if (periph->status == I2CIdle)
646  PPRZ_I2C_START_NEXT_TRANSACTION(periph);
647  /* else it will be started by the interrupt handler when the previous transactions completes */
648  __enable_irq();
649 
650  return TRUE;
651 }
652 
653 bool_t i2c_idle(struct i2c_periph* periph)
654 {
655  return PPRZ_I2C_IS_IDLE(periph);
656  //return periph->status == I2CIdle;
657 }
658 
659 
static void LED_ERROR(uint8_t nr)
Definition: i2c_attempt1.c:46
bool_t i2c_submit(struct i2c_periph *periph, struct i2c_transaction *t)
Definition: i2c_attempt1.c:628
I2CTransactionStatus
Definition: i2c.h:14
#define I2C1
Definition: LPC21xx.h:166
static void LED_INIT(void)
Definition: i2c_attempt1.c:32
void i2c_event(void)
Definition: i2c_arch.c:344
void * reg_addr
Definition: i2c.h:62
uint8_t trans_extract_idx
Definition: i2c.h:58
volatile uint16_t ack_fail_cnt
Definition: i2c.h:71
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Definition: i2c_attempt1.c:22
static void LED2_OFF(void)
Definition: i2c_attempt1.c:27
static void PPRZ_I2C_SEND_START(struct i2c_periph *periph)
bool_t i2c_idle(struct i2c_periph *periph)
Definition: i2c_attempt1.c:653
volatile uint8_t idx_buf
Definition: i2c.h:61
enum I2CStatus status
Definition: i2c.h:60
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Definition: i2c.h:43
#define FALSE
Definition: imu_chimu.h:141
volatile uint16_t smbus_alert_cnt
Definition: i2c.h:77
volatile uint16_t timeout_tlow_cnt
Definition: i2c.h:76
Definition: i2c.h:23
static void LED_STROBE2(void)
Definition: i2c_attempt1.c:60
volatile uint16_t miss_start_stop_cnt
Definition: i2c.h:72
unsigned long uint32_t
Definition: types.h:18
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Definition: i2c.h:78
static void i2c_error(struct i2c_periph *p)
Definition: i2c_arch.c:331
Definition: i2c.h:70
enum I2CTransactionStatus status
Definition: i2c.h:47
volatile uint16_t over_under_cnt
Definition: i2c.h:74
volatile uint16_t pec_recep_cnt
Definition: i2c.h:75
#define TRUE
Definition: imu_chimu.h:144
volatile uint32_t er_irq_cnt
Definition: i2c.h:80
volatile uint8_t buf[I2C_BUF_LEN]
Definition: i2c.h:46
uint8_t len_w
Definition: i2c.h:45
static void LED1_ON(void)
Definition: i2c_attempt1.c:12
uint16_t len_r
Definition: i2c.h:44
unsigned char uint8_t
Definition: types.h:14
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Definition: i2c.h:73
uint8_t trans_insert_idx
Definition: i2c.h:57
#define ZEROS_ERR_COUNTER(_i2c_err)
Definition: i2c.h:94
struct i2c_errors * errors
Definition: i2c.h:66
Definition: i2c.h:54
enum I2CTransactionType type
Definition: i2c.h:42
Definition: i2c.h:10
#define I2C_TRANSACTION_QUEUE_LEN
Definition: i2c.h:51
#define RESET
Definition: humid_sht.h:40
static void LED1_OFF(void)
Definition: i2c_attempt1.c:17
Definition: i2c.h:9
struct i2c_transaction * trans[I2C_TRANSACTION_QUEUE_LEN]
Definition: i2c.h:56