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i2c_arch.old.c
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1 #include "mcu_periph/i2c.h"
2 
3 #include <stm32/rcc.h>
4 #include <stm32/gpio.h>
5 #include <stm32/flash.h>
6 #include <stm32/misc.h>
7 
8 
9 static void start_transaction(struct i2c_periph* p);
10 static inline void end_of_transaction(struct i2c_periph *p);
11 static inline void i2c_hard_reset(struct i2c_periph *p);
12 static inline void i2c_reset_init(struct i2c_periph *p);
13 
14 #define I2C_BUSY 0x20
15 
16 #ifdef DEBUG_I2C
17 #define SPURIOUS_INTERRUPT(_status, _event) { while(1); }
18 #define OUT_OF_SYNC_STATE_MACHINE(_status, _event) { while(1); }
19 #else
20 #define SPURIOUS_INTERRUPT(_status, _event) {}
21 #define OUT_OF_SYNC_STATE_MACHINE(_status, _event) {}
22 #endif
23 
24 #ifdef USE_I2C1
25 static I2C_InitTypeDef I2C1_InitStruct = {
26  .I2C_Mode = I2C_Mode_I2C,
27  .I2C_DutyCycle = I2C_DutyCycle_2,
28  .I2C_OwnAddress1 = 0x00,
29  .I2C_Ack = I2C_Ack_Enable,
30  .I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit,
31  .I2C_ClockSpeed = 200000
32 };
33 #endif
34 
35 #ifdef USE_I2C2
36 static I2C_InitTypeDef I2C2_InitStruct = {
37  .I2C_Mode = I2C_Mode_I2C,
38  .I2C_DutyCycle = I2C_DutyCycle_2,
39  .I2C_OwnAddress1 = 0x00,
40  .I2C_Ack = I2C_Ack_Enable,
41  .I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit,
42  .I2C_ClockSpeed = 300000
43 };
44 #endif
45 
46 static inline void i2c_delay(void)
47 {
48  for (__IO int j = 0; j < 50; j++);
49 }
50 
51 static inline void i2c_apply_config(struct i2c_periph *p)
52 {
53  I2C_Init(p->reg_addr, p->init_struct);
54 }
55 
56 static inline void end_of_transaction(struct i2c_periph *p)
57 {
58  p->trans_extract_idx++;
60  p->trans_extract_idx = 0;
61  /* if we have no more transaction to process, stop here */
63  p->status = I2CIdle;
64  /* if not, start next transaction */
65  else
67 }
68 
69 static inline void abort_and_reset(struct i2c_periph *p) {
70  struct i2c_transaction* trans = p->trans[p->trans_extract_idx];
71  trans->status = I2CTransFailed;
72  I2C_ITConfig(p->reg_addr, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR, DISABLE);
73  i2c_hard_reset(p);
74  I2C_ITConfig(p->reg_addr, I2C_IT_ERR, ENABLE);
76 }
77 
78 #ifdef USE_I2C2
79 static inline void on_status_start_requested(struct i2c_periph *periph, struct i2c_transaction* trans, uint32_t event);
80 static inline void on_status_addr_wr_sent(struct i2c_periph *periph, struct i2c_transaction* trans, uint32_t event);
81 static inline void on_status_sending_byte(struct i2c_periph *periph, struct i2c_transaction* trans, uint32_t event);
82 static inline void on_status_stop_requested(struct i2c_periph *periph, struct i2c_transaction* trans, uint32_t event);
83 static inline void on_status_addr_rd_sent(struct i2c_periph *periph, struct i2c_transaction* trans, uint32_t event);
84 static inline void on_status_reading_byte(struct i2c_periph *periph, struct i2c_transaction* trans, uint32_t event);
85 static inline void on_status_reading_last_byte(struct i2c_periph *periph, struct i2c_transaction* trans, uint32_t event);
86 static inline void on_status_restart_requested(struct i2c_periph *periph, struct i2c_transaction* trans, uint32_t event);
87 
88 /*
89  * Start Requested
90  *
91  */
92 static inline void on_status_start_requested(struct i2c_periph *periph, struct i2c_transaction* trans, uint32_t event) {
93  if (event & I2C_FLAG_SB) {
94  if(trans->type == I2CTransRx) {
95  I2C_Send7bitAddress(periph->reg_addr, trans->slave_addr, I2C_Direction_Receiver);
96  periph->status = I2CAddrRdSent;
97  }
98  else {
99  I2C_Send7bitAddress(periph->reg_addr, trans->slave_addr, I2C_Direction_Transmitter);
100  periph->status = I2CAddrWrSent;
101  }
102  }
103  else
105 }
106 
107 /*
108  * Addr WR sent
109  *
110  */
111 static inline void on_status_addr_wr_sent(struct i2c_periph *periph, struct i2c_transaction* trans, uint32_t event) {
112  if ((event & I2C_FLAG_ADDR) && (event & I2C_FLAG_TRA)) {
113  I2C_SendData(periph->reg_addr, trans->buf[0]);
114  if (trans->len_w > 1) {
115  I2C_SendData(periph->reg_addr, trans->buf[1]);
116  periph->idx_buf = 2;
117  I2C_ITConfig(periph->reg_addr, I2C_IT_BUF, ENABLE);
118  periph->status = I2CSendingByte;
119  }
120  else {
121  periph->idx_buf = 1;
122  if (trans->type == I2CTransTx) {
123  I2C_GenerateSTOP(periph->reg_addr, ENABLE);
124  periph->status = I2CStopRequested;
125  }
126  else {
127  I2C_GenerateSTART(periph->reg_addr, ENABLE);
128  periph->status = I2CRestartRequested;
129  }
130  }
131  }
132  else
134 }
135 
136 /*
137  * Sending Byte
138  *
139  */
140 static inline void on_status_sending_byte(struct i2c_periph *periph, struct i2c_transaction* trans, uint32_t event) {
141  I2C_TypeDef *regs = (I2C_TypeDef *) periph->reg_addr;
142  if (event & I2C_FLAG_TXE) {
143  if (periph->idx_buf < trans->len_w) {
144  I2C_SendData(periph->reg_addr, trans->buf[periph->idx_buf]);
145  periph->idx_buf++;
146  }
147  else {
148  I2C_ITConfig(periph->reg_addr, I2C_IT_BUF, DISABLE);
149  if (trans->type == I2CTransTx) {
150  I2C_GenerateSTOP(periph->reg_addr, ENABLE);
151  /* Make sure that the STOP bit is cleared by Hardware */
152  static __IO uint8_t counter = 0;
153  while ((regs->CR1 & 0x200) == 0x200) {
154  counter++;
155  if (counter > 100) break;
156  }
157  periph->status = I2CStopRequested;
158  }
159  else {
160  I2C_GenerateSTART(periph->reg_addr, ENABLE);
161  periph->status = I2CRestartRequested;
162  }
163  }
164  }
165  else
167 }
168 
169 /*
170  * Stop Requested
171  *
172  */
173 static inline void on_status_stop_requested(struct i2c_periph *periph, struct i2c_transaction* trans, uint32_t event) {
174  /* bummer.... */
175  if (event & I2C_FLAG_RXNE) {
176  uint8_t read_byte = I2C_ReceiveData(periph->reg_addr);
177  if (periph->idx_buf < trans->len_r) {
178  trans->buf[periph->idx_buf] = read_byte;
179  }
180  }
181  I2C_ITConfig(periph->reg_addr, I2C_IT_EVT|I2C_IT_BUF, DISABLE); // should only need to disable evt, buf already disabled
182  trans->status = I2CTransSuccess;
183  end_of_transaction(periph);
184 }
185 
186 /*
187  * Addr RD sent
188  *
189  */
190 static inline void on_status_addr_rd_sent(struct i2c_periph *periph, struct i2c_transaction* trans, uint32_t event) {
191  I2C_TypeDef *regs = (I2C_TypeDef *) periph->reg_addr;
192 
193  if ((event & I2C_FLAG_ADDR) && !(event & I2C_FLAG_TRA)) {
194  periph->idx_buf = 0;
195  if(trans->len_r == 1) { // If we're going to read only one byte
196  I2C_AcknowledgeConfig(periph->reg_addr, DISABLE); // make sure it's gonna be nacked
197  I2C_GenerateSTOP(periph->reg_addr, ENABLE); // and followed by a stop
198  /* Make sure that the STOP bit is cleared by Hardware */
199  static __IO uint8_t counter = 0;
200  while ((regs->CR1 & 0x200) == 0x200) {
201  counter++;
202  if (counter > 100) break;
203  }
204  periph->status = I2CReadingLastByte; // and remember we did
205  }
206  else {
207  I2C_AcknowledgeConfig(periph->reg_addr, ENABLE); // if it's more than one byte, ack it
208  I2C_ITConfig(periph->reg_addr, I2C_IT_BUF, ENABLE);
209  periph->status = I2CReadingByte; // and remember we did
210  }
211  }
212  else
214 }
215 
216 
217 /*
218  * Reading byte
219  *
220  */
221 static inline void on_status_reading_byte(struct i2c_periph *periph, struct i2c_transaction* trans, uint32_t event) {
222  I2C_TypeDef *regs = (I2C_TypeDef *) periph->reg_addr;
223  if (event & I2C_FLAG_RXNE) {
224  uint8_t read_byte = I2C_ReceiveData(periph->reg_addr);
225  if (periph->idx_buf < trans->len_r) {
226  trans->buf[periph->idx_buf] = read_byte;
227  periph->idx_buf++;
228  if (periph->idx_buf >= trans->len_r-1) { // We're reading our last byte
229  I2C_AcknowledgeConfig(periph->reg_addr, DISABLE); // give them a nack once it's done
230  I2C_GenerateSTOP(periph->reg_addr, ENABLE); // and follow with a stop
231  /* Make sure that the STOP bit is cleared by Hardware */
232  static __IO uint8_t counter = 0;
233  while ((regs->CR1 & 0x200) == 0x200) {
234  counter++;
235  if (counter > 100) break;
236  }
237  periph->status = I2CStopRequested; // remember we already trigered the stop
238  }
239  } // else { something very wrong has happened }
240  }
241  else
243 }
244 
245 /*
246  * Reading last byte
247  *
248  */
249 static inline void on_status_reading_last_byte(struct i2c_periph *periph, struct i2c_transaction* trans, uint32_t event) {
250  if (event & I2C_FLAG_BTF) {
251  uint8_t read_byte = I2C_ReceiveData(periph->reg_addr);
252  trans->buf[periph->idx_buf] = read_byte;
253  I2C_GenerateSTOP(periph->reg_addr, ENABLE);
254  periph->status = I2CStopRequested;
255  }
256  else if (event & I2C_FLAG_RXNE) { // should really be BTF ?
257  uint8_t read_byte = I2C_ReceiveData(periph->reg_addr);
258  trans->buf[periph->idx_buf] = read_byte;
259  periph->status = I2CStopRequested;
260  }
261  else
263 }
264 
265 /*
266  * Restart requested
267  *
268  */
269 static inline void on_status_restart_requested(struct i2c_periph *periph, struct i2c_transaction* trans, uint32_t event) {
270  if (event & I2C_FLAG_SB) {
271  I2C_Send7bitAddress(periph->reg_addr, trans->slave_addr, I2C_Direction_Receiver);
272  periph->status = I2CAddrRdSent;
273  }
274 }
275 
276 
277 
278 static inline void i2c_event(struct i2c_periph *p, uint32_t event)
279 {
280  struct i2c_transaction* trans = p->trans[p->trans_extract_idx];
281  switch (p->status) {
282  case I2CStartRequested:
283  on_status_start_requested(p, trans, event);
284  break;
285  case I2CAddrWrSent:
286  on_status_addr_wr_sent(p, trans, event);
287  break;
288  case I2CSendingByte:
289  on_status_sending_byte(p, trans, event);
290  break;
291  case I2CStopRequested:
292  on_status_stop_requested(p, trans, event);
293  break;
294  case I2CAddrRdSent:
295  on_status_addr_rd_sent(p, trans, event);
296  break;
297  case I2CReadingByte:
298  on_status_reading_byte(p, trans, event);
299  break;
300  case I2CReadingLastByte:
301  on_status_reading_last_byte(p, trans, event);
302  break;
303  case I2CRestartRequested:
304  on_status_restart_requested(p, trans, event);
305  break;
306  default:
308  break;
309  }
310 }
311 
312 static inline void i2c_error(struct i2c_periph *p)
313 {
314  p->errors->er_irq_cnt;
315  if (I2C_GetITStatus(p->reg_addr, I2C_IT_AF)) { /* Acknowledge failure */
316  p->errors->ack_fail_cnt++;
317  I2C_ClearITPendingBit(p->reg_addr, I2C_IT_AF);
318  }
319  if (I2C_GetITStatus(p->reg_addr, I2C_IT_BERR)) { /* Misplaced Start or Stop condition */
321  I2C_ClearITPendingBit(p->reg_addr, I2C_IT_BERR);
322  }
323  if (I2C_GetITStatus(p->reg_addr, I2C_IT_ARLO)) { /* Arbitration lost */
324  p->errors->arb_lost_cnt++;
325  I2C_ClearITPendingBit(p->reg_addr, I2C_IT_ARLO);
326  // I2C_AcknowledgeConfig(I2C2, DISABLE);
327  // uint8_t dummy __attribute__ ((unused)) = I2C_ReceiveData(I2C2);
328  // I2C_GenerateSTOP(I2C2, ENABLE);
329  }
330  if (I2C_GetITStatus(p->reg_addr, I2C_IT_OVR)) { /* Overrun/Underrun */
331  p->errors->over_under_cnt++;
332  I2C_ClearITPendingBit(p->reg_addr, I2C_IT_OVR);
333  }
334  if (I2C_GetITStatus(p->reg_addr, I2C_IT_PECERR)) { /* PEC Error in reception */
335  p->errors->pec_recep_cnt++;
336  I2C_ClearITPendingBit(p->reg_addr, I2C_IT_PECERR);
337  }
338  if (I2C_GetITStatus(p->reg_addr, I2C_IT_TIMEOUT)) { /* Timeout or Tlow error */
339  p->errors->timeout_tlow_cnt++;
340  I2C_ClearITPendingBit(p->reg_addr, I2C_IT_TIMEOUT);
341  }
342  if (I2C_GetITStatus(p->reg_addr, I2C_IT_SMBALERT)) { /* SMBus alert */
343  p->errors->smbus_alert_cnt++;
344  I2C_ClearITPendingBit(p->reg_addr, I2C_IT_SMBALERT);
345  }
346 
347  abort_and_reset(p);
348 }
349 
350 
351 static inline void i2c_hard_reset(struct i2c_periph *p)
352 {
353  I2C_TypeDef *regs = (I2C_TypeDef *) p->reg_addr;
354 
355  I2C_DeInit(p->reg_addr);
356 
357  GPIO_InitTypeDef GPIO_InitStructure;
358  GPIO_InitStructure.GPIO_Pin = p->scl_pin | p->sda_pin;
359  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_10MHz;
360  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_OD;
361  GPIO_SetBits(GPIOB, p->scl_pin | p->sda_pin);
362  GPIO_Init(GPIOB, &GPIO_InitStructure);
363 
364  while(GPIO_ReadInputDataBit(GPIOB, p->sda_pin) == Bit_RESET) {
365  // Raise SCL, wait until SCL is high (in case of clock stretching)
366  GPIO_SetBits(GPIOB, p->scl_pin);
367  while (GPIO_ReadInputDataBit(GPIOB, p->scl_pin) == Bit_RESET);
368  i2c_delay();
369 
370  // Lower SCL, wait
371  GPIO_ResetBits(GPIOB, p->scl_pin);
372  i2c_delay();
373 
374  // Raise SCL, wait
375  GPIO_SetBits(GPIOB, p->scl_pin);
376  i2c_delay();
377  }
378 
379  // Generate a start condition followed by a stop condition
380  GPIO_SetBits(GPIOB, p->scl_pin);
381  i2c_delay();
382  GPIO_ResetBits(GPIOB, p->sda_pin);
383  i2c_delay();
384  GPIO_ResetBits(GPIOB, p->sda_pin);
385  i2c_delay();
386 
387  // Raise both SCL and SDA and wait for SCL high (in case of clock stretching)
388  GPIO_SetBits(GPIOB, p->scl_pin | p->sda_pin);
389  while (GPIO_ReadInputDataBit(GPIOB, p->scl_pin) == Bit_RESET);
390 
391  // Wait for SDA to be high
392  while (GPIO_ReadInputDataBit(GPIOB, p->sda_pin) != Bit_SET);
393 
394  // SCL and SDA should be high at this point, bus should be free
395  // Return the GPIO pins to the alternate function
396  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
397  GPIO_Init(GPIOB, &GPIO_InitStructure);
398 
399  I2C_DeInit(p->reg_addr);
400 
401  i2c_apply_config(p);
402 
403  if (regs->SR2 & I2C_BUSY) {
404  // Reset the I2C block
405  I2C_SoftwareResetCmd(p->reg_addr, ENABLE);
406  I2C_SoftwareResetCmd(p->reg_addr, DISABLE);
407  }
408 }
409 
410 static inline void i2c_reset_init(struct i2c_periph *p)
411 {
412  // Reset bus and configure GPIO pins
413  i2c_hard_reset(p);
414 
415  // enable peripheral
416  I2C_Cmd(p->reg_addr, ENABLE);
417 
418  // enable error interrupts
419  I2C_ITConfig(p->reg_addr, I2C_IT_ERR, ENABLE);
420 }
421 #endif
422 
423 #ifdef USE_I2C1
424 
425 struct i2c_errors i2c1_errors;
426 
427 #include "my_debug_servo.h"
428 
429 #define I2C1_ABORT_AND_RESET() { \
430  struct i2c_transaction* trans2 = i2c1.trans[i2c1.trans_extract_idx]; \
431  trans2->status = I2CTransFailed; \
432  I2C_ITConfig(I2C1, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR, DISABLE); \
433  I2C_Cmd(I2C1, DISABLE); \
434  I2C_DeInit(I2C1); \
435  I2C_Cmd(I2C1, ENABLE); \
436  i2c_apply_config(&i2c1); \
437  I2C_ITConfig(I2C1, I2C_IT_ERR, ENABLE); \
438  end_of_transaction(&i2c1); \
439  }
440 
441 //
442 // I2C1 base 0x40005400
443 //
444 // I2C1 CR1 0x40005400
445 // I2C1 CR2 0x40005404
446 //
447 // I2C2 base 0x40005800
448 //
449 
450 
451 void i2c1_hw_init(void) {
452 
453  i2c1.reg_addr = I2C1;
454  i2c1.init_struct = &I2C1_InitStruct;
455  i2c1.scl_pin = GPIO_Pin_6;
456  i2c1.sda_pin = GPIO_Pin_7;
457  i2c1.errors = &i2c1_errors;
458 
459  /* zeros error counter */
460  ZEROS_ERR_COUNTER(i2c1_errors);
461 
462  I2C_DeInit(I2C1);
463 
464  NVIC_PriorityGroupConfig(NVIC_PriorityGroup_0);
465  NVIC_InitTypeDef NVIC_InitStructure;
466 
467  /* Configure and enable I2C1 event interrupt -------------------------------*/
468  NVIC_InitStructure.NVIC_IRQChannel = I2C1_EV_IRQn;
469  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
470  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
471  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
472  NVIC_Init(&NVIC_InitStructure);
473 
474  /* Configure and enable I2C1 err interrupt -------------------------------*/
475  NVIC_InitStructure.NVIC_IRQChannel = I2C1_ER_IRQn;
476  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
477  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
478  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
479  NVIC_Init(&NVIC_InitStructure);
480 
481  /* Enable peripheral clocks --------------------------------------------------*/
482  /* Enable I2C1 clock */
483  RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2C1, ENABLE);
484  /* Enable GPIOB clock */
485  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
486 
487  /* Configure I2C1 pins: SCL and SDA ------------------------------------------*/
488  GPIO_InitTypeDef GPIO_InitStructure;
489  GPIO_StructInit(&GPIO_InitStructure);
490  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6 | GPIO_Pin_7;
491  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
492  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
493  GPIO_Init(GPIOB, &GPIO_InitStructure);
494 
495  /* I2C configuration ----------------------------------------------------------*/
496 
497  /* I2C Peripheral Enable */
498  I2C_Cmd(I2C1, ENABLE);
499  /* Apply I2C configuration after enabling it */
500  i2c_apply_config(&i2c1);
501 
502  /* Enable I2C1 error interrupts */
503  I2C_ITConfig(I2C1, I2C_IT_ERR, ENABLE);
504 
505 }
506 
507 
508 void i2c1_ev_irq_handler(void) {
509 
510  uint32_t event = I2C_GetLastEvent(I2C1);
511  struct i2c_transaction* trans = i2c1.trans[i2c1.trans_extract_idx];
512  switch (event) {
513  /* EV5 */
514  case I2C_EVENT_MASTER_MODE_SELECT:
515  if (trans->type == I2CTransTx || trans->type == I2CTransTxRx) {
516  /* Master Transmitter : Send slave Address for write */
517  I2C_Send7bitAddress(I2C1, (trans->slave_addr&0xFE), I2C_Direction_Transmitter);
518  }
519  else {
520  /* Master Receiver : Send slave Address for read */
521  I2C_Send7bitAddress(I2C1, (trans->slave_addr&0xFE), I2C_Direction_Receiver);
522  }
523  break;
524 
525  /* Master Transmitter --------------------------------------------------*/
526  /* Test on I2C1 EV6 and first EV8 and clear them */
527  case I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED:
528  /* enable empty dr if we have more than one byte to send */
529  // if (i2c1_len_w > 1)
530  I2C_ITConfig(I2C1, I2C_IT_BUF, ENABLE);
531  /* Send the first data */
532  I2C_SendData(I2C1, trans->buf[0]);
533  i2c1.idx_buf = 1;
534  break;
535 
536  /* Test on I2C1 EV8 and clear it */
537  case I2C_EVENT_MASTER_BYTE_TRANSMITTING: /* Without BTF, EV8 */
538  if(i2c1.idx_buf < trans->len_w) {
539  I2C_SendData(I2C1, trans->buf[i2c1.idx_buf]);
540  i2c1.idx_buf++;
541  }
542  else {
543  I2C_GenerateSTOP(I2C1, ENABLE);
544  // I2C_GenerateSTART(I2C1, ENABLE);
545  I2C_ITConfig(I2C1, I2C_IT_BUF, DISABLE);
546  }
547  break;
548 
549  case I2C_EVENT_MASTER_BYTE_TRANSMITTED: /* With BTF EV8-2 */
550  if(i2c1.idx_buf < trans->len_w) {
551  I2C_SendData(I2C1, trans->buf[i2c1.idx_buf]);
552  i2c1.idx_buf++;
553  }
554  else {
555  trans->status = I2CTransSuccess;
556  I2C_ITConfig(I2C1, I2C_IT_EVT, DISABLE);
557  end_of_transaction(&i2c1);
558  }
559  // while (I2C_GetFlagStatus(I2C1, I2C_FLAG_MSL));
560  break;
561 
562  default:
563  i2c1_errors.unexpected_event_cnt++;
564  i2c1_errors.last_unexpected_event = event;
565  // spurious Interrupt
566  // I have already had I2C_EVENT_SLAVE_STOP_DETECTED ( 0x10 )
567  // let's clear that by restarting I2C
568  // if (event == I2C_EVENT_SLAVE_STOP_DETECTED) {
569  // ok....? let's try that
570  I2C1_ABORT_AND_RESET();
571  break;
572  }
573 
574 }
575 
576 
577 void i2c1_er_irq_handler(void) {
578 
579  if (I2C_GetITStatus(I2C1, I2C_IT_AF)) { /* Acknowledge failure */
580  i2c1_errors.ack_fail_cnt++;
581  I2C_ClearITPendingBit(I2C1, I2C_IT_AF);
582  I2C_GenerateSTOP(I2C1, ENABLE);
583  }
584  if (I2C_GetITStatus(I2C1, I2C_IT_BERR)) { /* Misplaced Start or Stop condition */
585  i2c1_errors.miss_start_stop_cnt++;
586  I2C_ClearITPendingBit(I2C1, I2C_IT_BERR);
587  }
588  if (I2C_GetITStatus(I2C1, I2C_IT_ARLO)) { /* Arbitration lost */
589  i2c1_errors.arb_lost_cnt++;
590  I2C_ClearITPendingBit(I2C1, I2C_IT_ARLO);
591  }
592  if (I2C_GetITStatus(I2C1, I2C_IT_OVR)) { /* Overrun/Underrun */
593  i2c1_errors.over_under_cnt++;
594  I2C_ClearITPendingBit(I2C1, I2C_IT_OVR);
595  }
596  if (I2C_GetITStatus(I2C1, I2C_IT_PECERR)) { /* PEC Error in reception */
597  i2c1_errors.pec_recep_cnt++;
598  I2C_ClearITPendingBit(I2C1, I2C_IT_PECERR);
599  }
600  if (I2C_GetITStatus(I2C1, I2C_IT_TIMEOUT)) { /* Timeout or Tlow error */
601  i2c1_errors.timeout_tlow_cnt++;
602  I2C_ClearITPendingBit(I2C1, I2C_IT_TIMEOUT);
603  }
604  if (I2C_GetITStatus(I2C1, I2C_IT_SMBALERT)) { /* SMBus alert */
605  i2c1_errors.smbus_alert_cnt++;
606  I2C_ClearITPendingBit(I2C1, I2C_IT_SMBALERT);
607  }
608 
609  I2C1_ABORT_AND_RESET();
610 
611 }
612 
613 #endif /* USE_I2C1 */
614 
615 
616 
617 
618 
619 #ifdef USE_I2C2
620 
621 // dec hex
622 // 196609 30001 BUSY MSL | SB
623 // 458882 70082 TRA BUSY MSL | TXE ADDR
624 // 458884 70084 TRA BUSY MSL | TXE BTF
625 // 196609 30001 BUSY MSL | SB
626 // 196610 30002 BUSY MSL | ADDR
627 //
628 
629 
630 struct i2c_errors i2c2_errors;
631 
632 #include "my_debug_servo.h"
633 
634 void i2c2_hw_init(void) {
635 
636  i2c2.reg_addr = I2C2;
637  i2c2.init_struct = &I2C2_InitStruct;
638  i2c2.scl_pin = GPIO_Pin_10;
639  i2c2.sda_pin = GPIO_Pin_11;
640  i2c2.errors = &i2c2_errors;
641 
642  /* zeros error counter */
643  ZEROS_ERR_COUNTER(i2c2_errors);
644 
645  /* reset periphearl to default state ( sometimes not achieved on reset :( ) */
646  I2C_DeInit(I2C2);
647 
648  NVIC_PriorityGroupConfig(NVIC_PriorityGroup_0);
649  NVIC_InitTypeDef NVIC_InitStructure;
650 
651  /* Configure and enable I2C2 event interrupt --------------------------------*/
652  NVIC_InitStructure.NVIC_IRQChannel = I2C2_EV_IRQn;
653  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
654  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
655  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
656  NVIC_Init(&NVIC_InitStructure);
657 
658  /* Configure and enable I2C2 err interrupt ----------------------------------*/
659  NVIC_InitStructure.NVIC_IRQChannel = I2C2_ER_IRQn;
660  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
661  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
662  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
663  NVIC_Init(&NVIC_InitStructure);
664 
665  /* Enable peripheral clocks -------------------------------------------------*/
666  /* Enable I2C2 clock */
667  RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2C2, ENABLE);
668  /* Enable GPIOB clock */
669  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
670 
671  // Reset and initialize I2C HW
672  i2c_reset_init(&i2c2);
673 
674 }
675 
676 
677 
678 
679 void i2c2_ev_irq_handler(void) {
680  uint32_t event = I2C_GetLastEvent(I2C2);
681  i2c_event(&i2c2, event);
682 }
683 
684 void i2c2_er_irq_handler(void) {
685  i2c_error(&i2c2);
686 
687 }
688 
689 #endif /* USE_I2C2 */
690 
691 
692 
693 bool_t i2c_idle(struct i2c_periph* p)
694 {
695  return !I2C_GetFlagStatus(p->reg_addr, I2C_FLAG_BUSY);
696 }
697 
698 bool_t i2c_submit(struct i2c_periph* p, struct i2c_transaction* t) {
699 
700  uint8_t temp;
701  temp = p->trans_insert_idx + 1;
702  if (temp >= I2C_TRANSACTION_QUEUE_LEN) temp = 0;
703  if (temp == p->trans_extract_idx)
704  return FALSE; // queue full
705 
706  t->status = I2CTransPending;
707 
708 
709  __disable_irq();
710  /* put transacation in queue */
711  p->trans[p->trans_insert_idx] = t;
712  p->trans_insert_idx = temp;
713 
714  /* if peripheral is idle, start the transaction */
715  if (p->status == I2CIdle)
717  /* else it will be started by the interrupt handler when the previous transactions completes */
718  __enable_irq();
719 
720  return TRUE;
721 }
722 
723 
724 static void start_transaction(struct i2c_periph* p) {
725  p->idx_buf = 0;
727  // I2C_ZERO_EVENTS();
728  I2C_ITConfig(p->reg_addr, I2C_IT_EVT, ENABLE);
729  I2C_GenerateSTART(p->reg_addr, ENABLE);
730 }
static void on_status_reading_last_byte(struct i2c_periph *periph, struct i2c_transaction *trans, uint32_t event)
Definition: i2c_arch.c:266
#define I2C1
Definition: LPC21xx.h:166
static void i2c_hard_reset(struct i2c_periph *p)
static void on_status_restart_requested(struct i2c_periph *periph, struct i2c_transaction *trans, uint32_t event)
Definition: i2c_arch.c:286
void i2c_event(void)
Definition: i2c_arch.c:344
static void on_status_start_requested(struct i2c_periph *periph, struct i2c_transaction *trans, uint32_t event)
Definition: i2c_arch.c:105
void * reg_addr
Definition: i2c.h:62
uint8_t trans_extract_idx
Definition: i2c.h:58
static void on_status_stop_requested(struct i2c_periph *periph, struct i2c_transaction *trans, uint32_t event)
Definition: i2c_arch.c:190
volatile uint16_t ack_fail_cnt
Definition: i2c.h:71
static void start_transaction(struct i2c_periph *p)
Definition: i2c_arch.old.c:724
static void i2c_reset_init(struct i2c_periph *p)
#define I2C_BUSY
Definition: i2c_arch.old.c:14
static void on_status_sending_byte(struct i2c_periph *periph, struct i2c_transaction *trans, uint32_t event)
Definition: i2c_arch.c:157
static void on_status_addr_rd_sent(struct i2c_periph *periph, struct i2c_transaction *trans, uint32_t event)
Definition: i2c_arch.c:207
volatile uint8_t idx_buf
Definition: i2c.h:61
enum I2CStatus status
Definition: i2c.h:60
uint8_t slave_addr
Definition: i2c.h:43
#define FALSE
Definition: imu_chimu.h:141
volatile uint16_t smbus_alert_cnt
Definition: i2c.h:77
volatile uint16_t timeout_tlow_cnt
Definition: i2c.h:76
void * init_struct
Definition: i2c.h:63
Definition: i2c.h:23
volatile uint16_t miss_start_stop_cnt
Definition: i2c.h:72
#define OUT_OF_SYNC_STATE_MACHINE(_status, _event)
Definition: i2c_arch.old.c:21
uint16_t scl_pin
Definition: i2c.h:64
unsigned long uint32_t
Definition: types.h:18
uint16_t sda_pin
Definition: i2c.h:65
static void i2c_error(struct i2c_periph *p)
Definition: i2c_arch.c:331
#define SPURIOUS_INTERRUPT(_status, _event)
Definition: i2c_arch.old.c:20
Definition: i2c.h:70
enum I2CTransactionStatus status
Definition: i2c.h:47
static void abort_and_reset(struct i2c_periph *p)
Definition: i2c_arch.old.c:69
static void end_of_transaction(struct i2c_periph *p)
Definition: i2c_arch.old.c:56
volatile uint16_t over_under_cnt
Definition: i2c.h:74
static void i2c_apply_config(struct i2c_periph *p)
Definition: i2c_arch.old.c:51
volatile uint16_t pec_recep_cnt
Definition: i2c.h:75
#define TRUE
Definition: imu_chimu.h:144
volatile uint32_t er_irq_cnt
Definition: i2c.h:80
volatile uint8_t buf[I2C_BUF_LEN]
Definition: i2c.h:46
uint8_t len_w
Definition: i2c.h:45
uint16_t len_r
Definition: i2c.h:44
bool_t i2c_submit(struct i2c_periph *p, struct i2c_transaction *t)
Definition: i2c_arch.old.c:698
unsigned char uint8_t
Definition: types.h:14
volatile uint16_t arb_lost_cnt
Definition: i2c.h:73
uint8_t trans_insert_idx
Definition: i2c.h:57
#define ZEROS_ERR_COUNTER(_i2c_err)
Definition: i2c.h:94
struct i2c_errors * errors
Definition: i2c.h:66
Definition: i2c.h:54
enum I2CTransactionType type
Definition: i2c.h:42
Definition: i2c.h:10
bool_t i2c_idle(struct i2c_periph *p)
Definition: i2c_arch.old.c:693
static void on_status_reading_byte(struct i2c_periph *periph, struct i2c_transaction *trans, uint32_t event)
Definition: i2c_arch.c:238
#define I2C_TRANSACTION_QUEUE_LEN
Definition: i2c.h:51
static void on_status_addr_wr_sent(struct i2c_periph *periph, struct i2c_transaction *trans, uint32_t event)
Definition: i2c_arch.c:125
Definition: i2c.h:9
static void i2c_delay(void)
Definition: i2c_arch.old.c:46
struct i2c_transaction * trans[I2C_TRANSACTION_QUEUE_LEN]
Definition: i2c.h:56