Paparazzi UAS  v4.0.4_stable-3-gf39211a
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imu_crista_arch.c
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1 /*
2  * $Id$
3  *
4  * Copyright (C) 2008-2009 Antoine Drouin <poinix@gmail.com>
5  *
6  * This file is part of paparazzi.
7  *
8  * paparazzi is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2, or (at your option)
11  * any later version.
12  *
13  * paparazzi is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16  * GNU General Public License for more details.
17  *
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19  * along with paparazzi; see the file COPYING. If not, write to
20  * the Free Software Foundation, 59 Temple Place - Suite 330,
21  * Boston, MA 02111-1307, USA.
22  */
23 
24 #include "subsystems/imu.h"
25 
26 #include <stm32/gpio.h>
27 #include <stm32/rcc.h>
28 #include <stm32/spi.h>
29 #include <stm32/misc.h>
30 #include <stm32/dma.h>
31 
32 #include "stm32_vector_table.h"
33 
34 static volatile uint8_t channel;
35 static uint8_t buf_in[4];
36 static uint8_t buf_out[4];
37 
38 #define POWER_MODE (1 << 1 | 1)
39 #define SGL_DIF 1 // Single ended
40 
41 #define ADS8344Unselect() GPIOB->BSRR = GPIO_Pin_12
42 #define ADS8344Select() GPIOB->BRR = GPIO_Pin_12
43 
44 extern void dma1_c4_irq_handler(void);
45 static void ADS8344_read_channel( void );
46 
48 
49  channel = 0;
50  /* Enable SPI2 Periph clock -------------------------------------------------*/
51  RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);
52  /* Enable SPI_2 DMA clock ---------------------------------------------------*/
53  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
54  /* Enable PORTB GPIO clock --------------------------------------------------*/
55  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB | RCC_APB2Periph_AFIO , ENABLE);
56  /* Configure GPIOs: SCK, MISO and MOSI -------------------------------------*/
57  GPIO_InitTypeDef GPIO_InitStructure;
58  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
59  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
60  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
61  GPIO_Init(GPIOB, &GPIO_InitStructure);
62  /* set slave select as output and assert it ( on PB12) */
63  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;
64  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
65  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
66  GPIO_Init(GPIOB, &GPIO_InitStructure);
68  /* configure SPI after enabling it*/
69  SPI_Cmd(SPI2, ENABLE);
70  SPI_InitTypeDef SPI_InitStructure;
71  SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
72  SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
73  SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
74  SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
75  SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge;
76  SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
77  SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_16;
78  SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
79  SPI_InitStructure.SPI_CRCPolynomial = 7;
80  SPI_Init(SPI2, &SPI_InitStructure);
81 
82  /* Enable DMA1 channel4 IRQ Channel */
83  NVIC_InitTypeDef NVIC_init_struct = {
84  .NVIC_IRQChannel = DMA1_Channel4_IRQn,
85  .NVIC_IRQChannelPreemptionPriority = 0,
86  .NVIC_IRQChannelSubPriority = 0,
87  .NVIC_IRQChannelCmd = ENABLE
88  };
89  NVIC_Init(&NVIC_init_struct);
90 
91 }
92 
93 
94 void ADS8344_start( void ) {
95 
96  ADS8344Select();
97  channel = 0;
99 
100 }
101 
102 static void ADS8344_read_channel( void ) {
103 
104  // control byte
105  buf_out[0] = 1 << 7 | channel << 4 | SGL_DIF << 2 | POWER_MODE;
106 
107  /* trigger 4 bytes read */
108  /* SPI2_Rx_DMA_Channel configuration ------------------------------------*/
109  DMA_DeInit(DMA1_Channel4);
110  DMA_InitTypeDef DMA_initStructure_4 = {
111  .DMA_PeripheralBaseAddr = (uint32_t)(SPI2_BASE+0x0C),
112  .DMA_MemoryBaseAddr = (uint32_t)buf_in,
113  .DMA_DIR = DMA_DIR_PeripheralSRC,
114  .DMA_BufferSize = 4,
115  .DMA_PeripheralInc = DMA_PeripheralInc_Disable,
116  .DMA_MemoryInc = DMA_MemoryInc_Enable,
117  .DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte,
118  .DMA_MemoryDataSize = DMA_MemoryDataSize_Byte,
119  .DMA_Mode = DMA_Mode_Normal,
120  .DMA_Priority = DMA_Priority_VeryHigh,
121  .DMA_M2M = DMA_M2M_Disable
122  };
123  DMA_Init(DMA1_Channel4, &DMA_initStructure_4);
124 
125  /* SPI2_Tx_DMA_Channel configuration ------------------------------------*/
126  DMA_DeInit(DMA1_Channel5);
127  DMA_InitTypeDef DMA_initStructure_5 = {
128  .DMA_PeripheralBaseAddr = (uint32_t)(SPI2_BASE+0x0C),
129  .DMA_MemoryBaseAddr = (uint32_t)buf_out,
130  .DMA_DIR = DMA_DIR_PeripheralDST,
131  .DMA_BufferSize = 4,
132  .DMA_PeripheralInc = DMA_PeripheralInc_Disable,
133  .DMA_MemoryInc = DMA_MemoryInc_Enable,
134  .DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte,
135  .DMA_MemoryDataSize = DMA_MemoryDataSize_Byte,
136  .DMA_Mode = DMA_Mode_Normal,
137  .DMA_Priority = DMA_Priority_Medium,
138  .DMA_M2M = DMA_M2M_Disable
139  };
140  DMA_Init(DMA1_Channel5, &DMA_initStructure_5);
141 
142  /* Enable SPI_2 Rx request */
143  SPI_I2S_DMACmd(SPI2, SPI_I2S_DMAReq_Rx, ENABLE);
144  /* Enable DMA1 Channel4 */
145  DMA_Cmd(DMA1_Channel4, ENABLE);
146 
147  /* Enable SPI_2 Tx request */
148  SPI_I2S_DMACmd(SPI2, SPI_I2S_DMAReq_Tx, ENABLE);
149  /* Enable DMA1 Channel5 */
150  DMA_Cmd(DMA1_Channel5, ENABLE);
151 
152  /* Enable DMA1 Channel4 Transfer Complete interrupt */
153  DMA_ITConfig(DMA1_Channel4, DMA_IT_TC, ENABLE);
154 
155 }
156 
157 
159 
160  ADS8344_values[channel] = (buf_in[1] << 8 | buf_in[2]) << 1 | buf_in[3] >> 7;
161  channel++;
162  if (channel > 6) {
164  ADS8344Unselect();
165  DMA_ITConfig(DMA1_Channel4, DMA_IT_TC, DISABLE);
166  /* Disable SPI_2 Rx and TX request */
167  SPI_I2S_DMACmd(SPI2, SPI_I2S_DMAReq_Rx, DISABLE);
168  SPI_I2S_DMACmd(SPI2, SPI_I2S_DMAReq_Tx, DISABLE);
169  /* Disable DMA1 Channel4 and 5 */
170  DMA_Cmd(DMA1_Channel4, DISABLE);
171  DMA_Cmd(DMA1_Channel5, DISABLE);
172  }
173  else {
175  }
176 }
#define SGL_DIF
#define POWER_MODE
void dma1_c4_irq_handler(void)
uint16_t ADS8344_values[NB_CHANNELS]
Definition: ADS8344.c:41
bool_t ADS8344_available
Definition: ADS8344.c:40
void imu_crista_arch_init(void)
static uint8_t buf_in[4]
#define ADS8344Unselect()
unsigned long uint32_t
Definition: types.h:18
static volatile uint8_t channel
Inertial Measurement Unit interface.
#define TRUE
Definition: imu_chimu.h:144
void ADS8344_start(void)
unsigned char uint8_t
Definition: types.h:14
#define ADS8344Select()
static void ADS8344_read_channel(void)
static uint8_t buf_out[4]