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spi_slave_hs_arch.c
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2  * $Id$
3  *
4  * Copyright (C) 2011 The Paparazzi Team
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6  * This file is part of paparazzi.
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23 
24 #include "spi_slave_hs_arch.h"
25 #include "mcu_periph/spi.h"
26 
27 #include BOARD_CONFIG
28 #include "interrupt_hw.h"
29 #include "std.h"
30 #include "mcu.h"
31 #include "led.h"
32 #include "LPC21xx.h"
33 #include "ssp_hw.h"
34 #include "pprz_debug.h"
35 #include "armVIC.h"
36 
37 
38 /* High Speed SPI Slave Circular Buffer */
43 
44 /* Prototypes */
45 // void spi_init( void ); // -> declared in spi.h
46 static void SSP_ISR(void) __attribute__((naked));
47 
48 /* SSPCR0 settings */
49 #define SSP_DDS 0x07 << 0 /* data size : 8 bits */
50 //#define SSP_DDS 0x0F << 0 /* data size : 16 bits */
51 #define SSP_FRF 0x00 << 4 /* frame format : SPI */
52 #define SSP_CPOL 0x00 << 6 /* clock polarity : data captured on first clock transition */
53 #define SSP_CPHA 0x00 << 7 /* clock phase : SCK idles low */
54 #define SSP_SCR 0x00 << 8 /* serial clock rate : divide by 1 */
55 
56 #define SSPCR0_VAL (SSP_DDS | SSP_FRF | SSP_CPOL | SSP_CPHA | SSP_SCR )
57 
58 /* SSPCR1 settings */
59 #define SSP_LBM 0x00 << 0 /* loopback mode : disabled */
60 #define SSP_SSE 0x00 << 1 /* SSP enable : enable later when init ready */
61 #define SSP_MS 0x01 << 2 /* master slave mode : slave */
62 #define SSP_SOD 0x00 << 3 /* slave output disable : don't care when master */
63 
64 #define SSPCR1_VAL (SSP_LBM | SSP_SSE | SSP_MS | SSP_SOD )
65 
66 /* SSPCPSR settings
67  * min value as master: 2
68  * min value as slave: 12
69  */
70 #if (PCLK == 15000000)
71 #define CPSDVSR 12
72 #else
73 
74 #if (PCLK == 30000000)
75 #define CPSDVSR 24
76 #else
77 
78 #if (PCLK == 60000000)
79 #define CPSDVSR 28
80 #else
81 
82 #error unknown PCLK frequency
83 #endif
84 #endif
85 #endif
86 
87 #define SSP_PINSEL1_SCK (2<<2)
88 #define SSP_PINSEL1_MISO (2<<4)
89 #define SSP_PINSEL1_MOSI (2<<6)
90 #define SSP_PINSEL1_SSEL (2<<8)
91 
92 
93 #define SSP_Write(X) SSPDR=(X)
94 #define SSP_Read() SSPDR
95 #define SSP_Status() SSPSR
96 
97 void spi_init(void) {
98 
99  /* setup pins for SSP (SCK, MISO, MOSI) */
101 
102  /* setup SSP */
103  // Control Registers
104  SSPCR0 = SSPCR0_VAL;
105  SSPCR1 = SSPCR1_VAL;
106  // Clock Prescale Registers
107  SSPCPSR = CPSDVSR;
108 
109  /* initialize interrupt vector */
110  VICIntSelect &= ~VIC_BIT( VIC_SPI1 ); /* SPI1 selected as IRQ */
111  VICIntEnable = VIC_BIT( VIC_SPI1 ); /* enable it */
112  _VIC_CNTL(SSP_VIC_SLOT) = VIC_ENABLE | VIC_SPI1;
113  _VIC_ADDR(SSP_VIC_SLOT) = (uint32_t)SSP_ISR; /* address of the ISR */
114 
115 
116  // Enable SPI Slave
117  SetBit(SSPCR1, SSE);
118 
119  // Enable Receive interrupt
120  SetBit(SSPIMSC, RXIM);
121 
122 }
123 
124 /*
125  * SSP Status:
126  *
127  * ROVR Read Overrun
128  * WCOL Write Collision (send new byte during a transfer in progress
129  * ABRT SSEL inactive before end of transfer
130  *
131  *
132  */
133 
134 
135 static void SSP_ISR(void) {
136  ISR_ENTRY();
137 
138  //LED_TOGGLE(3);
139 
140  // If any TX bytes are pending
142  {
145  SSP_Write(ret);
146  }
147  else
148  {
149  SSP_Write(0x00);
150  }
151 
152 
153  //do
154  {
155  uint16_t temp;
156 
157  // calc next insert index & store character
160 
161  // check for more room in queue
162  if (temp != spi_slave_hs_rx_extract_idx)
163  spi_slave_hs_rx_insert_idx = temp; // update insert index
164 
165  // else overrun
166  }
167  // while FIFO not empty
168  //while (SSPSR & RNE);
169 
170 /*
171  // loop until not more interrupt sources
172  while (((iid = U0IIR) & UIIR_NO_INT) == 0)
173  while (U0LSR & ULSR_THRE)
174  {
175  // check if more data to send
176  if (uart0_tx_insert_idx != uart0_tx_extract_idx)
177  {
178  U0THR = uart0_tx_buffer[uart0_tx_extract_idx];
179  uart0_tx_extract_idx++;
180  uart0_tx_extract_idx %= UART0_TX_BUFFER_SIZE;
181  }
182  else
183  {
184  // no
185  uart0_tx_running = 0; // clear running flag
186  break;
187  }
188  }
189 
190 */
191  VICVectAddr = 0x00000000; /* clear this interrupt from the VIC */
192  ISR_EXIT();
193 }
194 
#define VICIntSelect
Definition: LPC21xx.h:398
unsigned short uint16_t
Definition: types.h:16
#define SSPCPSR
Definition: LPC21xx.h:226
#define _VIC_CNTL(idx)
Definition: armVIC.h:19
#define SSPCR0_VAL
uint8_t spi_slave_hs_rx_buffer[SPI_SLAVE_HS_RX_BUFFER_SIZE]
#define RXIM
Definition: LPC21xx.h:241
#define SSPCR1_VAL
#define SSP_PINSEL1_SSEL
#define SSPCR0
Definition: LPC21xx.h:222
uint16_t spi_slave_hs_rx_extract_idx
#define _VIC_ADDR(idx)
Definition: armVIC.h:20
arch independent SPI (Serial Peripheral Interface) API
void spi_init(void)
Definition: spi_arch.c:3
#define SSP_PINSEL1_SCK
#define SSP_Write(X)
#define SPI_SLAVE_HS_TX_BUFFER_SIZE
#define VICVectAddr
Definition: LPC21xx.h:404
unsigned long uint32_t
Definition: types.h:18
static void SSP_ISR(void)
uint8_t spi_slave_hs_tx_extract_idx
#define VIC_BIT(chan)
Definition: lpcVIC.h:105
uint8_t spi_slave_hs_tx_insert_idx
arch independent mcu ( Micro Controller Unit ) utilities
#define SPI_SLAVE_HS_RX_BUFFER_SIZE
unsigned char uint8_t
Definition: types.h:14
uint8_t spi_slave_hs_tx_buffer[SPI_SLAVE_HS_TX_BUFFER_SIZE]
#define ISR_EXIT()
Definition: armVIC.h:61
#define VICIntEnable
Definition: LPC21xx.h:399
#define PINSEL1
Definition: LPC21xx.h:316
#define SSP_PINSEL1_MOSI
#define VIC_SPI1
Definition: lpcVIC.h:81
arch independent LED (Light Emitting Diodes) API
#define SSP_PINSEL1_MISO
#define SSPCR1
Definition: LPC21xx.h:223
#define SSE
Definition: LPC21xx.h:234
#define SSP_Read()
uint16_t spi_slave_hs_rx_insert_idx
__attribute__((always_inline))
Definition: i2c_arch.c:35
#define SSPIMSC
Definition: LPC21xx.h:227
#define ISR_ENTRY()
Definition: armVIC.h:40
#define VIC_ENABLE
Definition: lpcVIC.h:102