Paparazzi UAS  v4.0.4_stable-3-gf39211a
Paparazzi is a free software Unmanned Aircraft System.
 All Data Structures Files Functions Variables Typedefs Enumerations Enumerator Macros Pages
max3100_hw.c
Go to the documentation of this file.
1 /*
2  * $Id$
3  *
4  * Copyright (C) 2009 ENAC
5  *
6  * This file is part of paparazzi.
7  *
8  * paparazzi is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2, or (at your option)
11  * any later version.
12  *
13  * paparazzi is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with paparazzi; see the file COPYING. If not, write to
20  * the Free Software Foundation, 59 Temple Place - Suite 330,
21  * Boston, MA 02111-1307, USA.
22  *
23  */
24 
25 #include "LPC21xx.h"
26 #include "interrupt_hw.h"
27 #include "max3100_hw.h"
28 
29 #include "ap_downlink.h"
30 #include "mcu_periph/uart.h"
31 
32 
34 bool volatile max3100_data_available;
36 
39 
42 
43 
44 bool read_bytes = false;
45 
46 
47 static void EXTINT_ISR(void) __attribute__((naked));
48 static void SPI1_ISR(void) __attribute__((naked));
49 
50 #define PINSEL1_SCK (2 << 2)
51 #define PINSEL1_MISO (2 << 4)
52 #define PINSEL1_MOSI (2 << 6)
53 #define PINSEL1_SSEL (2 << 8)
54 
55 /* SSPCR0 settings */
56 #define SSP_DSS 0x0F << 0 /* data size : 16 bits */
57 // #define SSP_DSS 0x07 << 0 /* data size : 8 bits */
58 #define SSP_FRF 0x00 << 4 /* frame format : SPI */
59 #define SSP_CPOL 0x00 << 6 /* clock polarity : idle low */
60 #define SSP_CPHA 0x00 << 7 /* clock phase : 0 */
61 #define SSP_SCR 0x0F << 8 /* serial clock rate : 29.3kHz, SSP input clock / 16 */
62 
63 /* SSPCR1 settings */
64 #define SSP_LBM 0x00 << 0 /* loopback mode : disabled */
65 #define SSP_SSE 0x00 << 1 /* SSP enable : disabled */
66 #define SSP_MS 0x00 << 2 /* master slave mode : master */
67 #define SSP_SOD 0x00 << 3 /* slave output disable : don't care when master */
68 
69 #ifndef SSPCPSR_VAL
70 #define SSPCPSR_VAL 0x04
71 #endif
72 
73 
74 void max3100_init( void ) {
76  max3100_data_available = false;
82 
83  /* setup pins for SSP (SCK, MISO, MOSI) */
85 
86  /* setup SSP */
89  SSPCPSR = SSPCPSR_VAL; /* Prescaler */
90 
91 
92  /* From arm7/max1167_hw.c */
93 
94  /* SS pin is output */
96  /* unselected max3100 */
98 
99  /* connect extint (IRQ) */
100  MAX3100_IRQ_PINSEL |= MAX3100_IRQ_PINSEL_VAL << MAX3100_IRQ_PINSEL_BIT;
101  /* extint is edge trigered */
102  SetBit(EXTMODE, MAX3100_IRQ_EINT);
103  /* extint is trigered on falling edge */
104  ClearBit(EXTPOLAR, MAX3100_IRQ_EINT);
105  /* clear pending extint0 before enabling interrupts */
106  SetBit(EXTINT, MAX3100_IRQ_EINT);
107 
108  /* Configure interrupt vector for external pin interrupt */
109  VICIntSelect &= ~VIC_BIT( MAX3100_VIC_EINT ); // EXTINT selected as IRQ
110  VICIntEnable = VIC_BIT( MAX3100_VIC_EINT ); // EXTINT interrupt enabled
111  VICVectCntl8 = VIC_ENABLE | MAX3100_VIC_EINT;
112  VICVectAddr8 = (uint32_t)EXTINT_ISR; // address of the ISR
113 
114  /* Configure interrupt vector for SPI */
115  VICIntSelect &= ~VIC_BIT(VIC_SPI1); /* SPI1 selected as IRQ */
116  VICIntEnable = VIC_BIT(VIC_SPI1); /* SPI1 interrupt enabled */
118  VICVectAddr7 = (uint32_t)SPI1_ISR; /* address of the ISR */
119 
120  /* Write configuration */
121  //Max3100TransmitConf(MAX3100_BAUD_RATE | MAX3100_BIT_NOT_TM);
123 }
124 
125 
126 /******* External interrupt: Data input available ***********/
127 void EXTINT_ISR(void) {
128  ISR_ENTRY();
129 
130  max3100_data_available = true;
131 
132  SetBit(EXTINT, MAX3100_IRQ_EINT); /* clear extint */
133  VICVectAddr = 0x00000000; /* clear this interrupt from the VIC */
134 
135  ISR_EXIT();
136 }
137 
138 void SPI1_ISR(void) {
139  ISR_ENTRY();
140 
141  while (bit_is_set(SSPSR, RNE)) {
142  uint16_t data = SSPDR;
143 
144  if (bit_is_set(data, MAX3100_R_BIT)) { /* Data available */
145  max3100_rx_buf[max3100_rx_insert_idx] = data & 0xff;
146  max3100_rx_insert_idx++; // automatic overflow because len=256
147  read_bytes = true;
148  }
149  if (bit_is_set(data, MAX3100_T_BIT) && (max3100_status == MAX3100_STATUS_READING)) { /* transmit buffer empty */
151  }
152  }
153  SpiClearRti(); /* clear interrupt */
154  SpiDisableRti();
155  SpiDisable ();
156  Max3100Unselect();
158 
159  VICVectAddr = 0x00000000; /* clear this interrupt from the VIC */
160  ISR_EXIT();
161 }
162 
163 void max3100_debug(void) {
164  /*** DOWNLINK_SEND_DEBUG(DefaultChannel, DefaultDevice, 16, max3100_rx_buf); ***/
165 }
#define SSPCPSR_VAL
#define VICIntSelect
Definition: LPC21xx.h:398
unsigned short uint16_t
Definition: types.h:16
#define Max3100TransmitConf(_conf)
Definition: max3100_hw.h:114
arch independent UART (Universal Asynchronous Receiver/Transmitter) API
uint8_t volatile max3100_tx_insert_idx
Definition: max3100_hw.c:37
#define SSP_MS
#define SpiDisableRti()
Definition: spi_arch.h:80
#define SSPCPSR
Definition: LPC21xx.h:226
#define Max3100Unselect()
Definition: max3100_hw.h:63
bool volatile max3100_data_available
Definition: max3100_hw.c:34
#define EXTMODE
Definition: LPC21xx.h:387
#define MAX3100_TX_BUF_LEN
I/O Buffers.
Definition: max3100_hw.h:47
uint8_t volatile max3100_status
Definition: max3100_hw.c:33
uint8_t volatile max3100_rx_extract_idx
Definition: max3100_hw.c:38
uint8_t volatile max3100_tx_buf[MAX3100_TX_BUF_LEN]
Definition: max3100_hw.c:40
#define SSPCR0
Definition: LPC21xx.h:222
#define SpiClearRti()
Definition: spi_arch.h:84
void SPI1_ISR(void)
Definition: max3100_hw.c:138
#define SSP_SOD
#define MAX3100_R_BIT
Definition: max3100_hw.h:88
uint8_t volatile max3100_tx_extract_idx
Definition: max3100_hw.c:37
bool read_bytes
Definition: max3100_hw.c:44
#define VICVectAddr8
Definition: LPC21xx.h:414
#define MAX3100_BIT_NOT_TM
Definition: max3100_hw.h:85
#define EXTPOLAR
Definition: LPC21xx.h:388
#define EXTINT
Definition: LPC21xx.h:385
bool volatile max3100_transmit_buffer_empty
Definition: max3100_hw.c:35
#define SSP_DSS
#define SSPSR
Definition: LPC21xx.h:225
#define MAX3100_T_BIT
Definition: max3100_hw.h:87
#define PINSEL1_MOSI
#define VICVectAddr
Definition: LPC21xx.h:404
#define PINSEL1_SCK
unsigned long uint32_t
Definition: types.h:18
void max3100_debug(void)
Definition: max3100_hw.c:163
#define SSP_FRF
#define MAX3100_SS_PIN
Definition: max3100_hw.h:28
#define SSP_CPOL
#define VIC_BIT(chan)
Definition: lpcVIC.h:105
#define RNE
Definition: LPC21xx.h:247
#define SSP_CPHA
#define SSP_LBM
static void EXTINT_ISR(void)
Definition: max3100_hw.c:47
uint8_t volatile max3100_rx_buf[MAX3100_RX_BUF_LEN]
Definition: max3100_hw.c:41
#define VICVectCntl8
Definition: LPC21xx.h:430
#define SSP_SCR
unsigned char uint8_t
Definition: types.h:14
#define SpiDisable()
Definition: spi_arch.h:72
#define SSPDR
Definition: LPC21xx.h:224
#define ISR_EXIT()
Definition: armVIC.h:61
#define MAX3100_BIT_NOT_RM
Definition: max3100_hw.h:84
#define MAX3100_STATUS_IDLE
Max3100 protocol status.
Definition: max3100_hw.h:38
#define MAX3100_STATUS_READING
Definition: max3100_hw.h:40
#define VICIntEnable
Definition: LPC21xx.h:399
void max3100_init(void)
#define PINSEL1
Definition: LPC21xx.h:316
#define VICVectAddr7
Definition: LPC21xx.h:413
#define VIC_SPI1
Definition: lpcVIC.h:81
#define MAX3100_SS_IODIR
Definition: max3100_hw.h:34
#define PINSEL1_MISO
#define SSPCR1
Definition: LPC21xx.h:223
#define MAX3100_RX_BUF_LEN
Definition: max3100_hw.h:48
__attribute__((always_inline))
Definition: i2c_arch.c:35
#define ISR_ENTRY()
Definition: armVIC.h:40
uint8_t volatile max3100_rx_insert_idx
Definition: max3100_hw.c:38
#define VIC_ENABLE
Definition: lpcVIC.h:102
#define VICVectCntl7
Definition: LPC21xx.h:429