Paparazzi UAS  v4.0.4_stable-3-gf39211a
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imu_b2_arch.c
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1 /*
2  * $Id$
3  *
4  * Copyright (C) 2008-2009 Antoine Drouin <poinix@gmail.com>
5  *
6  * This file is part of paparazzi.
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23 
24 #include "subsystems/imu.h"
25 
26 int imu_overrun = 0;
28 static void SSP_ISR(void) __attribute__((naked));
29 
30 /* SSPCR0 settings */
31 #define SSP_DDS8 0x07 << 0 /* data size : 8 bits */
32 #define SSP_DDS16 0x0F << 0 /* data size : 16 bits */
33 #define SSP_FRF 0x00 << 4 /* frame format : SPI */
34 #define SSP_CPOL 0x00 << 6 /* clock polarity : data captured on first clock transition */
35 #define SSP_CPHA 0x00 << 7 /* clock phase : SCK idles low */
36 #define SSP_SCR 0x0F << 8 /* serial clock rate : divide by 16 */
37 
38 /* SSPCR1 settings */
39 #define SSP_LBM 0x00 << 0 /* loopback mode : disabled */
40 #define SSP_SSE 0x00 << 1 /* SSP enable : disabled */
41 #define SSP_MS 0x00 << 2 /* master slave mode : master */
42 #define SSP_SOD 0x00 << 3 /* slave output disable : don't care when master */
43 
44 #define SSPCR0_VAL8 (SSP_DDS8 | SSP_FRF | SSP_CPOL | SSP_CPHA | SSP_SCR )
45 #define SSPCR0_VAL16 (SSP_DDS16 | SSP_FRF | SSP_CPOL | SSP_CPHA | SSP_SCR )
46 #define SSPCR1_VAL (SSP_LBM | SSP_SSE | SSP_MS | SSP_SOD )
47 
48 #define SSP_PINSEL1_SCK (2<<2)
49 #define SSP_PINSEL1_MISO (2<<4)
50 #define SSP_PINSEL1_MOSI (2<<6)
51 
52 
53 #define ImuSetSSP8bits() { \
54  SSPCR0 = SSPCR0_VAL8; \
55 }
56 
57 #define ImuSetSSP16bits() { \
58  SSPCR0 = SSPCR0_VAL16; \
59 }
60 
61 
62 void imu_b2_arch_init(void) {
63 
65 
66  /* setup pins for SSP (SCK, MISO, MOSI) */
68 
69  /* setup SSP */
72  SSPCPSR = 0x02;
73 
74  /* initialize interrupt vector */
75  VICIntSelect &= ~VIC_BIT( VIC_SPI1 ); /* SPI1 selected as IRQ */
76  VICIntEnable = VIC_BIT( VIC_SPI1 ); /* enable it */
77  _VIC_CNTL(SSP_VIC_SLOT) = VIC_ENABLE | VIC_SPI1;
78  _VIC_ADDR(SSP_VIC_SLOT) = (uint32_t)SSP_ISR; /* address of the ISR */
79 
80 }
81 
82 
83 void imu_periodic(void) {
84  // check ssp idle
86  {
87  imu_overrun++;
88  return; //, DEBUG_IMU, IMU_ERR_OVERUN);
89  }
90 
91  // setup 16 bits
93  // read adc
95  max1168_read();
96 #if defined IMU_B2_MAG_TYPE && IMU_B2_MAG_TYPE == IMU_B2_MAG_AMI601
97  RunOnceEvery(10, { ami601_read(); });
98 #endif
99 #if defined IMU_B2_MAG_TYPE && IMU_B2_MAG_TYPE == IMU_B2_MAG_HMC58XX
100  RunOnceEvery(5,Hmc58xxPeriodic());
101 #endif
102 
103 }
104 
105 
106 
107 #if defined IMU_B2_MAG_TYPE && IMU_B2_MAG_TYPE == IMU_B2_MAG_MS2100
108 
109 static void SSP_ISR(void) {
110  ISR_ENTRY();
111 
112  switch (imu_ssp_status) {
114  Max1168OnSpiInt();
116  ImuSetSSP8bits();
117  if (ms2100_status == MS2100_IDLE) {
118  Ms2100SendReq();
119  }
120  else { /* MS2100_GOT_EOC */
121  Ms2100ReadRes();
122  }
124  }
125  else {
127  }
128  break;
130  Ms2100OnSpiInt();
131  if (ms2100_status == MS2100_IDLE) {
132  Ms2100SendReq();
134  }
135  else
137  break;
138 
139  // default:
140  // spurious interrupt
141  // FIXME LED_ON(1);
142  }
143 
144  VICVectAddr = 0x00000000; /* clear this interrupt from the VIC */
145  ISR_EXIT();
146 }
147 
148 #else //no IMU_B2_MAG_MS2100
149 
150 static void SSP_ISR(void) {
151  ISR_ENTRY();
152 
153  switch (imu_ssp_status) {
155  Max1168OnSpiInt();
157  break;
158 
159  // default:
160  // spurious interrupt
161  // FIXME LED_ON(1);
162  }
163 
164  VICVectAddr = 0x00000000; /* clear this interrupt from the VIC */
165  ISR_EXIT();
166 }
167 
168 #endif //no IMU_B2_MAG_MS2100
#define VICIntSelect
Definition: LPC21xx.h:398
#define IMU_SSP_STA_IDLE
Definition: imu_b2_arch.c:33
void imu_periodic(void)
Definition: imu_b2_arch.c:83
volatile uint8_t imu_ssp_status
Definition: imu_b2_arch.c:27
#define SSPCPSR
Definition: LPC21xx.h:226
#define _VIC_CNTL(idx)
Definition: armVIC.h:19
#define Max1168OnSpiInt()
Definition: max1168_arch.h:60
#define SSPCR1_VAL
#define SSPCR0
Definition: LPC21xx.h:222
#define _VIC_ADDR(idx)
Definition: armVIC.h:20
#define Ms2100SendReq()
Definition: ms2100_arch.h:62
#define MS2100_GOT_EOC
Definition: ms2100.h:39
#define IMU_SSP_STA_BUSY_MAX1168
Definition: imu_b2_arch.c:34
#define VICVectAddr
Definition: LPC21xx.h:404
unsigned long uint32_t
Definition: types.h:18
volatile uint8_t ms2100_status
Definition: ms2100.c:26
#define SSP_PINSEL1_MISO
static void SSP_ISR(void)
Definition: imu_b2_arch.c:28
void imu_b2_arch_init(void)
Definition: imu_b2_arch.c:42
#define IMU_SSP_STA_BUSY_MS2100
Definition: imu_b2_arch.c:35
Inertial Measurement Unit interface.
#define VIC_BIT(chan)
Definition: lpcVIC.h:105
#define SSPCR0_VAL16
#define SSP_PINSEL1_SCK
unsigned char uint8_t
Definition: types.h:14
#define ISR_EXIT()
Definition: armVIC.h:61
void ami601_read(void)
Definition: ami601.c:25
int imu_overrun
Definition: imu_b2_arch.c:26
#define VICIntEnable
Definition: LPC21xx.h:399
#define PINSEL1
Definition: LPC21xx.h:316
#define ImuSetSSP8bits()
#define VIC_SPI1
Definition: lpcVIC.h:81
#define SSPCR1
Definition: LPC21xx.h:223
void max1168_read(void)
Definition: max1168_arch.c:52
#define Ms2100OnSpiInt()
Definition: ms2100_arch.h:25
#define Hmc58xxPeriodic()
Definition: hmc58xx.h:91
#define ImuSetSSP16bits()
__attribute__((always_inline))
Definition: i2c_arch.c:35
#define SSP_PINSEL1_MOSI
#define ISR_ENTRY()
Definition: armVIC.h:40
#define MS2100_IDLE
Definition: ms2100.h:35
#define Ms2100ReadRes()
Definition: ms2100_arch.h:75
#define VIC_ENABLE
Definition: lpcVIC.h:102