Paparazzi UAS  v4.0.4_stable-3-gf39211a
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spi_arch.h
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3  * Copyright (C) 2003-2005 Pascal Brisset, Antoine Drouin
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23 
28 #ifndef SPI_ARCH_H
29 #define SPI_ARCH_H
30 
31 #include "std.h"
32 #include "LPC21xx.h"
33 #include BOARD_CONFIG
34 
35 extern volatile uint8_t spi_tx_idx;
36 extern volatile uint8_t spi_rx_idx;
37 
38 #define SpiInitBuf() { \
39  spi_rx_idx = 0; \
40  spi_tx_idx = 0; \
41  spi_message_received = FALSE; \
42  SpiTransmit(); /* fill fifo */ \
43 }
44 
45 #define SpiTransmit() { \
46  while (spi_tx_idx < spi_buffer_length \
47  && bit_is_set(SSPSR, TNF)) { \
48  SpiSend(spi_buffer_output[spi_tx_idx]); \
49  spi_tx_idx++; \
50  } \
51  if (spi_tx_idx == spi_buffer_length) \
52  SpiDisableTxi(); \
53 }
54 
55 #define SpiReceive() { \
56  while (bit_is_set(SSPSR, RNE)) { \
57  if (spi_rx_idx < spi_buffer_length) { \
58  SpiRead(spi_buffer_input[spi_rx_idx]) \
59  spi_rx_idx++; \
60  } \
61  else { \
62  uint8_t foo; \
63  SpiRead(foo); \
64  } \
65  } \
66  }
67 
68 #define SpiEnable() { \
69  SetBit(SSPCR1, SSE); \
70  }
71 
72 #define SpiDisable() { \
73  ClearBit(SSPCR1, SSE); \
74  }
75 
76 #define SpiEnableRti() { \
77  SetBit(SSPIMSC, RTIM); \
78  }
79 
80 #define SpiDisableRti() { \
81  ClearBit(SSPIMSC, RTIM); \
82  }
83 
84 #define SpiClearRti() { \
85  SetBit(SSPICR, RTIC); \
86  }
87 
88 #define SpiEnableTxi() { \
89  SetBit(SSPIMSC, TXIM); \
90  }
91 
92 #define SpiDisableTxi() { \
93  ClearBit(SSPIMSC, TXIM); \
94  }
95 
96 #define SpiEnableRxi() { \
97  SetBit(SSPIMSC, RXIM); \
98  }
99 
100 #define SpiDisableRxi() { \
101  ClearBit(SSPIMSC, RXIM); \
102  }
103 
104 #define SpiSend(a) { \
105  SSPDR = a; \
106  }
107 
108 #define SpiRead(a) { \
109  a = SSPDR; \
110  }
111 
112 #ifdef SPI_SLAVE
113 #define SpiStart() { \
114  SpiEnable(); \
115  SpiInitBuf(); \
116  SpiEnableTxi(); /* enable tx fifo half empty interrupt */ \
117  }
118 
119 #endif /* SPI_SLAVE */
120 
121 
122 
123 #ifdef SPI_MASTER
124 
125 
126 /* !!!!!!!!!!!!! Code for one single slave at a time !!!!!!!!!!!!!!!!! */
127 #if defined SPI_SELECT_SLAVE1_PIN && defined SPI_SELECT_SLAVE0_PIN
128 #error "SPI: one single slave, please"
129 #endif
130 
131 
132 #define SpiStart() { \
133  SpiEnable(); \
134  SpiInitBuf(); \
135  SpiEnableTxi(); /* enable tx fifo half empty interrupt */ \
136 }
137 
138 /*
139  * Slave0 select : P0.20 PINSEL1 00 << 8
140  * Slave1 select : P1.20
141  *
142  */
143 
144 #define SPI_SELECT_SLAVE_IO__(port, reg) IO ## port ## reg
145 #define SPI_SELECT_SLAVE_IO_(port, reg) SPI_SELECT_SLAVE_IO__(port, reg)
146 
147 #define SPI_SELECT_SLAVE0_IODIR SPI_SELECT_SLAVE_IO_(SPI_SELECT_SLAVE0_PORT, DIR)
148 #define SPI_SELECT_SLAVE0_IOCLR SPI_SELECT_SLAVE_IO_(SPI_SELECT_SLAVE0_PORT, CLR)
149 #define SPI_SELECT_SLAVE0_IOSET SPI_SELECT_SLAVE_IO_(SPI_SELECT_SLAVE0_PORT, SET)
150 
151 #define SPI_SELECT_SLAVE1_IODIR SPI_SELECT_SLAVE_IO_(SPI_SELECT_SLAVE1_PORT, DIR)
152 #define SPI_SELECT_SLAVE1_IOCLR SPI_SELECT_SLAVE_IO_(SPI_SELECT_SLAVE1_PORT, CLR)
153 #define SPI_SELECT_SLAVE1_IOSET SPI_SELECT_SLAVE_IO_(SPI_SELECT_SLAVE1_PORT, SET)
154 
155 
156 #define SpiSelectSlave0() { \
157  spi_cur_slave = SPI_SLAVE0; \
158  SetBit(SPI_SELECT_SLAVE0_IOCLR, SPI_SELECT_SLAVE0_PIN); \
159  }
160 
161 #define SpiUnselectSlave0() { \
162  spi_cur_slave = SPI_NONE; \
163  SetBit(SPI_SELECT_SLAVE0_IOSET, SPI_SELECT_SLAVE0_PIN); \
164  }
165 
166 
167 #define SpiSelectSlave1() { \
168  spi_cur_slave = SPI_SLAVE1; \
169  SetBit(SPI_SELECT_SLAVE1_IOCLR, SPI_SELECT_SLAVE1_PIN); \
170  }
171 
172 #define SpiUnselectSlave1() { \
173  spi_cur_slave = SPI_NONE; \
174  SetBit(SPI_SELECT_SLAVE1_IOSET, SPI_SELECT_SLAVE1_PIN); \
175  }
176 
177 #ifdef SPI_SELECT_SLAVE0_PIN
178 #define SpiUnselectCurrentSlave() SpiUnselectSlave0()
179 #endif
180 
181 #ifdef SPI_SELECT_SLAVE1_PIN
182 #define SpiUnselectCurrentSlave() SpiUnselectSlave1()
183 #endif
184 
185 #endif /* SPI_MASTER */
186 
187 
188 #define SpiSetCPOL() (SSPCR0 |= _BV(6))
189 #define SpiClrCPOL() (SSPCR0 &= ~(_BV(6)))
190 
191 #define SpiSetCPHA() (SSPCR0 |= _BV(7))
192 #define SpiClrCPHA() (SSPCR0 &= ~(_BV(7)))
193 
194 
195 #endif /* SPI_ARCH_H */
unsigned char uint8_t
Definition: types.h:14
volatile uint8_t spi_rx_idx
Definition: spi_arch.c:35
volatile uint8_t spi_tx_idx
handling of arm7 SPI hardware for now only SPI1 ( aka SSP )
Definition: spi_arch.c:34