Paparazzi UAS  v4.0.4_stable-3-gf39211a
Paparazzi is a free software Unmanned Aircraft System.
 All Data Structures Files Functions Variables Typedefs Enumerations Enumerator Macros Pages
i2c_attempt4_nodouble_isr.c
Go to the documentation of this file.
1 #include "mcu_periph/i2c.h"
2 
3 #include <stm32/rcc.h>
4 #include <stm32/gpio.h>
5 #include <stm32/flash.h>
6 #include <stm32/misc.h>
7 
8 #define I2C_DEBUG_LED
9 
11 // TODO: remove this
12 
13 
14 #ifdef I2C_DEBUG_LED
15 
16 static inline void LED1_ON(void)
17 {
18  GPIO_WriteBit(GPIOB, GPIO_Pin_6 , Bit_SET );
19 }
20 
21 static inline void LED1_OFF(void)
22 {
23  GPIO_WriteBit(GPIOB, GPIO_Pin_6 , !Bit_SET );
24 }
25 
26 static inline void LED2_ON(void)
27 {
28  GPIO_WriteBit(GPIOB, GPIO_Pin_7 , Bit_SET );
29 }
30 
31 static inline void LED2_OFF(void)
32 {
33  GPIO_WriteBit(GPIOB, GPIO_Pin_7 , !Bit_SET );
34 }
35 
36 static inline void LED_INIT(void)
37 {
38  GPIO_InitTypeDef GPIO_InitStructure;
39  RCC_APB2PeriphClockCmd( RCC_APB2Periph_GPIOB, ENABLE);
40  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_6;
41  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
42  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
43  GPIO_Init(GPIOB, &GPIO_InitStructure);
44 
45  LED1_OFF();
46  LED2_OFF();
47 }
48 
49 
50 static inline void LED_ERROR(uint8_t base, uint8_t nr)
51 {
52  LED2_ON();
53  for (int i=0;i<(base+nr);i++)
54  {
55  LED1_ON();
56  LED1_OFF();
57  }
58  LED2_OFF();
59 }
60 #endif
61 
64 
65 #ifdef USE_I2C1
66 static I2C_InitTypeDef I2C1_InitStruct = {
67  .I2C_Mode = I2C_Mode_I2C,
68  .I2C_DutyCycle = I2C_DutyCycle_2,
69  .I2C_OwnAddress1 = 0x00,
70  .I2C_Ack = I2C_Ack_Enable,
71  .I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit,
72  .I2C_ClockSpeed = 40000
73 };
74 #endif
75 
76 #ifdef USE_I2C2
77 static I2C_InitTypeDef I2C2_InitStruct = {
78  .I2C_Mode = I2C_Mode_I2C,
79  .I2C_DutyCycle = I2C_DutyCycle_2,
80  .I2C_OwnAddress1 = 0x00,
81  .I2C_Ack = I2C_Ack_Enable,
82  .I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit,
83 // .I2C_ClockSpeed = 37000
84  .I2C_ClockSpeed = 400000
85 };
86 #endif
87 
90 
91 // Bypassing the libSTM I2C functions to have more control over the reading of registers
92 // e.g. SR1 and SR2 should not always be read together as it might unwantedly clear ADDR flags etc.
93 
94 // Referring to STM32 manual:
95 // -Doc ID 13902 Rev 11
96 
97 // Status Register 1
98 
99 #define I2C_SR1_BIT_SB (1<<0) // Start Condition Met
100 #define I2C_SR1_BIT_ADDR (1<<1) // Address Sent
101 #define I2C_SR1_BIT_BTF (1<<2) // SCL held low
102 #define I2C_SR1_BIT_RXNE (1<<6) // Data Read Available
103 #define I2C_SR1_BIT_TXE (1<<7) // TX buffer space available
104 
105 #define I2C_SR1_BIT_ERR_BUS (1<<8) // Misplaced Start/Stop (usually interference)
106 #define I2C_SR1_BIT_ERR_ARLO (1<<9) // Arbitration Lost (in multimaster) or SDA short-to-ground (in single master)
107 #define I2C_SR1_BIT_ERR_AF (1<<10) // Ack Failure (too fast/too soon/no sensor/wiring break/...)
108 #define I2C_SR1_BIT_ERR_OVR (1<<11) // Overrun [data loss] (in slave) or SCL short-to-ground (in single master)
109 
110 #define I2C_SR1_BITS_ERR ((1<<8)|(1<<9)|(1<<10)|(1<<11)|(1<<12)|(1<<14)|(1<<15))
111 
112 // Status Register 2
113 
114 #define I2C_SR2_BIT_TRA (1<<2) // Transmitting
115 #define I2C_SR2_BIT_BUSY (1<<1) // Busy
116 #define I2C_SR2_BIT_MSL (1<<0) // Master Selected
117 
118 // Control Register 1
119 
120 #define I2C_CR1_BIT_PE (1<<0) // Peripheral Enable
121 #define I2C_CR1_BIT_START (1<<8) // Generate a Start
122 #define I2C_CR1_BIT_STOP (1<<9) // Generate a Stop
123 #define I2C_CR1_BIT_ACK (1<<10) // ACK / NACK
124 #define I2C_CR1_BIT_POS (1<<11) // Ack will control not the next but secondnext received byte
125 #define I2C_CR1_BIT_SWRST (1<<15) // Clear Busy Condition when no stop was detected
126 
127 // Control Register 2
128 
129 #define I2C_CR2_BIT_ITERREN (1<<8) // Error Interrupt
130 #define I2C_CR2_BIT_ITEVTEN (1<<9) // Event Interrupt
131 #define I2C_CR2_BIT_ITBUFEN (1<<10) // Buffer Interrupt
132 
133 
134 // Bit Control
135 
136 #define BIT_X_IS_SET_IN_REG(X,REG) (((REG) & (X)) == (X))
137 
138 // Critical Zones
139 
140 #define __I2C_REG_CRITICAL_ZONE_START
141 #define __I2C_REG_CRITICAL_ZONE_STOP
142 
143 
146 
147 // TODO: remove debug
148 #ifdef I2C_DEBUG_LED
149 
150 static inline void LED_SHOW_ACTIVE_BITS(I2C_TypeDef *regs)
151 {
152  uint16_t CR1 = regs->CR1;
153  uint16_t SR1 = regs->SR1;
154  uint16_t SR2 = regs->SR2;
155  // Note: reading SR1 and then SR2 will clear ADDR bits
156 
157  LED1_ON();
158 
159  // 1 Start
160  if (BIT_X_IS_SET_IN_REG( I2C_SR1_BIT_SB, SR1 ) )
161  LED2_ON();
162  else
163  LED2_OFF();
164  LED2_OFF();
165 
166  // 2 Addr
168  LED2_ON();
169  else
170  LED2_OFF();
171  LED2_OFF();
172 
173  // 3 BTF
175  LED2_ON();
176  else
177  LED2_OFF();
178  LED2_OFF();
179 
180  // 4 ERROR
181  if (( SR1 & I2C_SR1_BITS_ERR ) != 0x0000)
182  LED2_ON();
183  else
184  LED2_OFF();
185  LED2_OFF();
186 
187  // Anything?
188  if (( SR1 + SR2) != 0x0000)
189  LED2_ON();
190  else
191  LED2_OFF();
192  LED2_OFF();
193 
194  LED1_OFF();
195 
196 
197  LED1_ON();
198 
199  // 1 Start
201  LED2_ON();
202  else
203  LED2_OFF();
204  LED2_OFF();
205 
206  // 2 Stop
208  LED2_ON();
209  else
210  LED2_OFF();
211  LED2_OFF();
212 
213  // 3 Busy
215  LED2_ON();
216  else
217  LED2_OFF();
218  LED2_OFF();
219 
220  // 4 Tra
222  LED2_ON();
223  else
224  LED2_OFF();
225  LED2_OFF();
226 
227  // 5 Master
229  LED2_ON();
230  else
231  LED2_OFF();
232  LED2_OFF();
233  LED1_OFF();
234 
235 //#define I2C_DEBUG_LED_CONTROL
236 #ifdef I2C_DEBUG_LED_CONTROL
237 
238 
239  LED1_ON();
240 
241  // 1 Anything CR?
242  if (( CR1) != 0x0000)
243  LED2_ON();
244  else
245  LED2_OFF();
246  LED2_OFF();
247 
248  // 2 PE
249  if (BIT_X_IS_SET_IN_REG( I2C_CR1_BIT_PE, CR1 ) )
250  LED2_ON();
251  else
252  LED2_OFF();
253  LED2_OFF();
254 
255  // 3 SWRESET
257  LED2_ON();
258  else
259  LED2_OFF();
260  LED2_OFF();
261 
262  LED1_OFF();
263 #endif
264 
265 }
266 #endif
267 
268 static inline void PPRZ_I2C_SEND_STOP(I2C_TypeDef *regs)
269 {
270  // Man: p722: Stop generation after the current byte transfer or after the current Start condition is sent.
271  regs->CR1 |= I2C_CR1_BIT_STOP;
272 
273 #ifdef I2C_DEBUG_LED
274  LED2_ON();
275  LED1_ON();
276  LED1_OFF();
277  LED2_OFF();
278 #endif
279 }
280 
281 // (RE)START
282 
283 static inline void PPRZ_I2C_SEND_START(struct i2c_periph *periph)
284 {
285  I2C_TypeDef *regs = (I2C_TypeDef *) periph->reg_addr;
286 
287  periph->idx_buf = 0;
288 
289 #ifdef I2C_DEBUG_LED
290  LED_SHOW_ACTIVE_BITS(regs);
291 
292  LED2_ON();
293  LED1_ON();
294  LED1_OFF();
295  LED1_ON();
296  LED1_OFF();
297  LED1_ON();
298  LED1_OFF();
299  LED2_OFF();
300 
301 #endif
302 
303 /*
304  if (BIT_X_IS_SET_IN_REG( I2C_CR1_BIT_STOP, regs->CR1 ) )
305  {
306  regs->CR1 &= ~ I2C_CR1_BIT_STOP;
307  }
308 */
309 
310  // Enable Error IRQ, Event IRQ but disable Buffer IRQ
311  regs->CR2 |= I2C_CR2_BIT_ITERREN;
312  regs->CR2 |= I2C_CR2_BIT_ITEVTEN;
313  regs->CR2 &= ~ I2C_CR2_BIT_ITBUFEN;
314 
315  // Issue a new start
316  regs->CR1 = (I2C_CR1_BIT_START | I2C_CR1_BIT_PE);
317  periph->status = I2CStartRequested;
318 
319 
320 #ifdef I2C_DEBUG_LED
321  LED_SHOW_ACTIVE_BITS(regs);
322 #endif
323 }
324 
325 // STOP
326 
329 //
330 // SUBTRANSACTION SEQUENCES
331 
337 };
338 
339 static inline enum STMI2CSubTransactionStatus stmi2c_send(I2C_TypeDef *regs, struct i2c_periph *periph, struct i2c_transaction *trans)
340 {
341  uint16_t SR1 = regs->SR1;
342 
343  // Start Condition Was Just Generated
344  if (BIT_X_IS_SET_IN_REG( I2C_SR1_BIT_SB, SR1 ) )
345  {
346  // Disable buffer interrupt
347  regs->CR2 &= ~ I2C_CR2_BIT_ITBUFEN;
348  // Send Slave address and wait for ADDR interrupt
349  regs->DR = trans->slave_addr;
350  }
351  // Address Was Sent
352  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BIT_ADDR, SR1) )
353  {
354  // Now read SR2 to clear the ADDR
355  uint16_t SR2 __attribute__ ((unused)) = regs->SR2;
356 
357  // Maybe check we are transmitting (did not loose arbitration for instance)
358  // if (! BIT_X_IS_SET_IN_REG(I2C_SR2_BIT_TRA, SR2)) { }
359 
360  // Send First max 2 bytes
361  regs->DR = trans->buf[0];
362  if (trans->len_w > 1)
363  {
364  regs->DR = trans->buf[1];
365  periph->idx_buf = 2;
366  }
367  else
368  {
369  periph->idx_buf = 1;
370  }
371 
372  // Enable buffer-space available interrupt
373  // only if there is more to send: wait for TXE, no more to send: wait for BTF
374  if ( periph->idx_buf < trans->len_w)
375  regs->CR2 |= I2C_CR2_BIT_ITBUFEN;
376  }
377  // The buffer is not full anymore AND we were not waiting for BTF
379  {
380  // Send the next byte
381  regs->DR = trans->buf[periph->idx_buf];
382  periph->idx_buf++;
383 
384  // All bytes Sent? Then wait for BTF instead
385  if ( periph->idx_buf >= trans->len_w)
386  {
387  // Not interested anymore to know the buffer has space left
388  regs->CR2 &= ~ I2C_CR2_BIT_ITBUFEN;
389  // Next interrupt will be BTF (or error)
390  }
391  }
392  // BTF: means last byte was sent
393  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BIT_BTF, SR1) )
394  {
395  if (trans->type == I2CTransTx)
396  {
397  // Tell the driver we are ready
398  trans->status = I2CTransSuccess;
399  }
400 
401  return STMI2C_SubTra_Ready;
402  }
403  else // Hardware error
404  {
405  return STMI2C_SubTra_Error;
406  }
407 
408  return STMI2C_SubTra_Busy;
409 }
410 
411 static inline enum STMI2CSubTransactionStatus stmi2c_read1(I2C_TypeDef *regs, struct i2c_transaction *trans)
412 {
413  uint16_t SR1 = regs->SR1;
414 
415  // Start Condition Was Just Generated
416  if (BIT_X_IS_SET_IN_REG( I2C_SR1_BIT_SB, SR1 ) )
417  {
418  regs->CR2 &= ~ I2C_CR2_BIT_ITBUFEN;
419  regs->DR = trans->slave_addr | 0x01;
420  }
421  // Address Was Sent
422  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BIT_ADDR, SR1) )
423  {
424  // First Clear the ACK bit: after the next byte we do not want new bytes
425  regs->CR1 &= ~ I2C_CR1_BIT_POS;
426  regs->CR1 &= ~ I2C_CR1_BIT_ACK;
427 
428  // --- next to steps MUST be executed together to avoid missing the stop
430 
431  // Only after setting ACK, read SR2 to clear the ADDR (next byte will start arriving)
432  uint16_t SR2 __attribute__ ((unused)) = regs->SR2;
433 
434  // Schedule a Stop
435  PPRZ_I2C_SEND_STOP(regs);
436 
438  // --- end of critical zone -----------
439 
440  // Enable the RXNE to get the result
441  regs->CR2 |= I2C_CR2_BIT_ITBUFEN;
442  }
443  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BIT_RXNE, SR1) )
444  {
445  regs->CR2 &= ~ I2C_CR2_BIT_ITBUFEN;
446  trans->buf[0] = regs->DR;
447 
448  // We got all the results (stop condition might still be in progress but this is the last interrupt)
449  trans->status = I2CTransSuccess;
450 
452  }
453  else // Hardware error
454  {
455  return STMI2C_SubTra_Error;
456  }
457 
458  return STMI2C_SubTra_Busy;
459 }
460 
461 static inline enum STMI2CSubTransactionStatus stmi2c_read2(I2C_TypeDef *regs, struct i2c_transaction *trans)
462 {
463  uint16_t SR1 = regs->SR1;
464 
465  // Start Condition Was Just Generated
466  if (BIT_X_IS_SET_IN_REG( I2C_SR1_BIT_SB, SR1 ) )
467  {
468  regs->CR2 &= ~ I2C_CR2_BIT_ITBUFEN;
469  regs->CR1 |= I2C_CR1_BIT_ACK;
470  regs->CR1 |= I2C_CR1_BIT_POS;
471  regs->DR = trans->slave_addr | 0x01;
472  }
473  // Address Was Sent
474  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BIT_ADDR, SR1) )
475  {
476  // BEFORE clearing ACK, read SR2 to clear the ADDR (next byte will start arriving)
477  // clearing ACK after the byte transfer has already started will NACK the next (2nd)
478  uint16_t SR2 __attribute__ ((unused)) = regs->SR2;
479 
480  // --- make absolutely sure this command is not delayed too much after the previous:
482  // if transfer of DR was finished already then we will get too many bytes
483  // NOT First Clear the ACK bit but only AFTER clearing ADDR
484  regs->CR1 &= ~ I2C_CR1_BIT_ACK;
485 
486  // Disable the RXNE and wait for BTF
487  regs->CR2 &= ~ I2C_CR2_BIT_ITBUFEN;
488 
490  // --- end of critical zone -----------
491  }
492  // Receive buffer if full, master is halted: BTF
493  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BIT_BTF, SR1) )
494  {
495  // Stop condition MUST be set BEFORE reading the DR
496  // otherwise since there is new buffer space a new byte will be read
497  PPRZ_I2C_SEND_STOP(regs);
498 
499  trans->buf[0] = regs->DR;
500  trans->buf[1] = regs->DR;
501 
502  // We got all the results
503  trans->status = I2CTransSuccess;
504 
506  }
507  else // Hardware error
508  {
509  return STMI2C_SubTra_Error;
510  }
511 
512  return STMI2C_SubTra_Busy;
513 }
514 
515 static inline enum STMI2CSubTransactionStatus stmi2c_readmany(I2C_TypeDef *regs, struct i2c_periph *periph, struct i2c_transaction *trans)
516 {
517  uint16_t SR1 = regs->SR1;
518 
519  // Start Condition Was Just Generated
520  if (BIT_X_IS_SET_IN_REG( I2C_SR1_BIT_SB, SR1 ) )
521  {
522  regs->CR2 &= ~ I2C_CR2_BIT_ITBUFEN;
523  // The first data byte will be acked in read many so the slave knows it should send more
524  regs->CR1 &= ~ I2C_CR1_BIT_POS;
525  regs->CR1 |= I2C_CR1_BIT_ACK;
526  // Clear the SB flag
527  regs->DR = trans->slave_addr | 0x01;
528  }
529  // Address Was Sent
530  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BIT_ADDR, SR1) )
531  {
532  periph->idx_buf = 0;
533 
534  // Enable RXNE: receive an interrupt any time a byte is available
535  // only enable if MORE than 3 bytes need to be read
536  if (periph->idx_buf < (trans->len_r - 3))
537  {
538  regs->CR2 |= I2C_CR2_BIT_ITBUFEN;
539  }
540 
541  // ACK is still on to get more DATA
542  // Read SR2 to clear the ADDR (next byte will start arriving)
543  uint16_t SR2 __attribute__ ((unused)) = regs->SR2;
544  }
545  // one or more bytes are available AND we were interested in Buffer interrupts
547  {
548  // read byte until 3 bytes remain to be read (e.g. len_r = 6, -> idx=3 means idx 3,4,5 = 3 remain to be read
549  if (periph->idx_buf < (trans->len_r - 3))
550  {
551  trans->buf[periph->idx_buf] = regs->DR;
552  periph->idx_buf ++;
553  }
554  // from : 3bytes -> last byte: do nothing
555  //
556  // finally: this was the last byte
557  else if (periph->idx_buf >= (trans->len_r - 1))
558  {
559  regs->CR2 &= ~ I2C_CR2_BIT_ITBUFEN;
560 
561  // Last Value
562  trans->buf[periph->idx_buf] = regs->DR;
563  periph->idx_buf ++;
564 
565  // We got all the results
566  trans->status = I2CTransSuccess;
567 
569  }
570 
571  // Check for end of transaction: start waiting for BTF instead of RXNE
572  if (periph->idx_buf < (trans->len_r - 3))
573  {
574  regs->CR2 |= I2C_CR2_BIT_ITBUFEN;
575  }
576  else // idx >= len-3: there are 3 bytes to be read
577  {
578  // We want to halt I2C to have sufficient time to clear ACK, so:
579  // Stop listening to RXNE as it will be triggered infinitely since we did not empty the buffer
580  // on the next (second in buffer) received byte BTF will be set (buffer full and I2C halted)
581  regs->CR2 &= ~ I2C_CR2_BIT_ITBUFEN;
582  }
583  }
584  // Buffer is full while this was not a RXNE interrupt
585  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BIT_BTF, SR1) )
586  {
587  // Now the shift register and data register contain data(n-2) and data(n-1)
588  // And I2C is halted so we have time
589 
590  // --- Make absolutely sure the next 2 I2C actions are performed with no delay
592 
593  // First we clear the ACK while the SCL is held low by BTF
594  regs->CR1 &= ~ I2C_CR1_BIT_ACK;
595 
596  // Now that ACK is cleared we read one byte: instantly the last byte is being clocked in...
597  trans->buf[periph->idx_buf] = regs->DR;
598  periph->idx_buf ++;
599 
600  // Now the last byte is being clocked. Stop in MUST be set BEFORE the transfer of the last byte is complete
601  PPRZ_I2C_SEND_STOP(regs);
602 
604  // --- end of critical zone -----------
605 
606  // read the byte2 we had in the buffer (BTF means 2 bytes available)
607  trans->buf[periph->idx_buf] = regs->DR;
608  periph->idx_buf ++;
609 
610  // Ask for an interrupt to read the last byte (which is normally still busy now)
611  // The last byte will be received with RXNE
612  regs->CR2 |= I2C_CR2_BIT_ITBUFEN;
613  }
614  else // Hardware error
615  {
616  // Error
617 #ifdef I2C_DEBUG_LED
618  LED2_ON();
619  LED1_ON();
620  LED2_OFF();
621  LED1_OFF();
622 #endif
623  return STMI2C_SubTra_Error;
624  }
625 
626  return STMI2C_SubTra_Busy;
627 }
628 
629 
630 static inline void stmi2c_clear_pending_interrupts(I2C_TypeDef *regs)
631 {
632  uint16_t SR1 = regs->SR1;
633 
634  regs->CR2 &= ~ I2C_CR2_BIT_ITBUFEN; // Disable TXE, RXNE
635 
636  //regs->CR1 &= ~ I2C_CR1_BIT_PE; // Disable Periferial
637  //regs->CR1 |= I2C_CR1_BIT_PE; // Enable Periferial
638 
639  // Start Condition Was Generated
640  if (BIT_X_IS_SET_IN_REG( I2C_SR1_BIT_SB, SR1 ) )
641  {
642  // SB: cleared by software when reading SR1 and writing to DR
643  regs->DR = 0x00;
644  }
645  // Address Was Sent
647  {
648  // ADDR: Cleared by software when reading SR1 and then SR2
649  uint16_t SR2 __attribute__ ((unused)) = regs->SR2;
650  }
651  // Byte Transfer Finished
653  {
654  // SB: cleared by software when reading SR1 and reading/writing to DR
655  uint8_t dummy __attribute__ ((unused)) = regs->DR;
656  regs->DR = 0x00;
657  }
658 
659 
660  // Still have a start sheduled
661 // if (BIT_X_IS_SET_IN_REG(I2C_CR1_BIT_START, regs->CR1) )
662  {
663  // Clear pending start conditions
664 // regs->CR1 &= ~ I2C_CR1_BIT_START;
665  }
666 
667 }
668 
669 
670 static inline void i2c_error(struct i2c_periph *periph);
671 
672 static inline void i2c_irq(struct i2c_periph *periph)
673 {
674 
675  /*
676  There are 7 possible reasons to get here:
677 
678  If IT_EV_FEN
679  -------------------------
680 
681  We are always interested in all IT_EV_FEV: all are required.
682 
683  1) SB // Start Condition Success in Master mode
684  2) ADDR // Address sent received Acknoledge
685  [3 ADDR10] // -- 10bit address stuff
686  [4 STOPF] // -- only for slaves: master has no stop interrupt
687  5) BTF // I2C has stopped working (it is waiting for new data, all buffers are tx_empty/rx_full)
688 
689  // Beware: using the buffered I2C has some interesting properties:
690  -in master receive mode: BTF only occurs after the 2nd received byte: after the first byte is received it is
691  in RD but the I2C can still receive a second byte. Only when the 2nd byte is received while the RxNE is 1
692  then a BTF occurs (I2C can not continue receiving bytes or they will get lost). During BTF I2C is halted (SCL held low)
693  -in master transmitmode: when writing a byte to WD, you instantly get a new TxE interrupt while the first is not
694  transmitted yet. The byte was pushed to the I2C shift register and the buffer is ready for more. You can already
695  fill new data in the buffer while the first is still being transmitted for max performance transmission.
696 
697  // Beware: besides data buffering you can/must plan several consecutive actions. You can send 2 bytes to the buffer, ask for a stop and
698  a new start in one go.
699 
700  -thanks to / because of this buffering and event sheduling there is not 1 interrupt per start / byte / stop
701  This also means you must think more in advance and a transaction could be popped from the stack even before it is
702  actually completely transmitted. But then you would not know the result yet so you have to keep it until the result
703  is known.
704 
705  // Beware: the order in which Status is read determines how flags are cleared. You should not just read SR1 & SR2 every time
706 
707  If IT_EV_FEN AND IT_EV_BUF
708  --------------------------
709 
710  Buffer event are not always wanted and are tipically switched on during longer data transfers. Make sure to turn off in time.
711 
712  6) RxNE
713  7) TxE
714 
715  --------------------------------------------------------------------------------------------------
716  // This driver uses only a subset of the pprz_i2c_states for several reasons:
717  // -we have less interrupts than the I2CStatus states (for efficiency)
718  // -STM32 has such a powerfull I2C engine with plenty of status register flags that
719  only little extra status information needs to be stored.
720 
721  // Status is re-used (abused) to remember the last COMMAND THAT WAS SENT to the STM I2C hardware.
722 
723 // TODO: check which are used
724  enum I2CStatus {
725  I2CIdle, // No more last command
726 
727  I2CStartRequested, // Last command was start
728  I2CRestartRequested, // Last command was restart
729  I2CStopRequested, // Very important to not send double stop conditions
730 
731  I2CSendingByte, // Some address/data operation
732 
733  // Following are not used
734  I2CReadingByte,
735  I2CAddrWrSent,
736  I2CAddrRdSent,
737  I2CSendingLastByte,
738  I2CReadingLastByte,
739  I2CComplete,
740  I2CFailed
741  };
742 
743  ---------
744 
745  The STM waits indefinately (holding SCL low) for user interaction:
746  a) after a master-start (waiting for address)
747  b) after an address (waiting for data)
748  not during data sending when using buffered
749  c) after the last byte is transmitted (waiting for either stop or restart)
750  not during data receiving when using buffered
751  not after the last byte is received
752 
753  -The STM I2C stalls indefinately when a stop condition was attempted that
754  did not succeed. The BUSY flag remains on.
755  -There is no STOP interrupt: use needs another way to finish.
756 
757  */
758 
759 
761  // Reading the status:
762  // - Caution: this clears several flags and can start transmissions etc...
763  // - Certain flags like STOP / (N)ACK need to be guaranteed to be set before
764  // the transmission of the byte is finished. At higher clock rates that can be
765  // quite fast: so we allow no other interrupt to be triggered in between
766  // reading the status and setting all needed flags
767 
768  // Direct Access to the I2C Registers
769  // Do not read SR2 as it might start the reading while an (n)ack bit might be needed first
770  I2C_TypeDef *regs = (I2C_TypeDef *) periph->reg_addr;
771 
772 #ifdef I2C_DEBUG_LED
773  LED1_ON();
774  LED1_OFF();
775 #endif
776 
777 
780  //
781  // TRANSACTION HANDLER
782 
783  enum STMI2CSubTransactionStatus ret = 0;
784 
786  // Nothing Left To Do
787  if (periph->trans_extract_idx == periph->trans_insert_idx)
788  {
789 #ifdef I2C_DEBUG_LED
790  LED2_ON();
791  LED1_ON();
792  LED2_OFF();
793  LED1_OFF();
794 
795  // no transaction and also an error?
796  LED_SHOW_ACTIVE_BITS(regs);
797 #endif
798 
799  // If we still get an interrupt but there are no more things to do
800  // (which can happen if an event was sheduled just before a bus error occurs)
801  // then its easy: just stop: clear all interrupt generating bits
802 
803  // Count The Errors
804  i2c_error(periph);
805 
806  // Clear Running Events
808 
809  // Mark this as a special error
810  periph->errors->unexpected_event_cnt++;
811 
812  periph->status = I2CIdle;
813 
814  // There are no transactions anymore:
815  // furtheron we need a transaction pointer: so we are not allowed to continue
816  return;
817  }
818 
819  struct i2c_transaction* trans = periph->trans[periph->trans_extract_idx];
820 
822  // If there was an error:
823  if (( regs->SR1 & I2C_SR1_BITS_ERR ) != 0x0000)
824  {
825 
826 #ifdef I2C_DEBUG_LED
827  LED1_ON();
828  LED2_ON();
829  LED1_OFF();
830  LED2_OFF();
831 
832  LED_SHOW_ACTIVE_BITS(regs);
833 #endif
834 
835  // Set result in transaction
836  trans->status = I2CTransFailed;
837 
838  // Prepare for next
839  ret = STMI2C_SubTra_Ready;
840 
841  // Make sure a TxRx does not Restart
842  trans->type = I2CTransRx;
843 
844 /*
845  // There are 2 types of errors: some need a STOP, some better do without: Following will not get an extra stop
846  if (
847  // Lost Arbitration
848  (BIT_X_IS_SET_IN_REG( I2C_SR1_BIT_ERR_ARLO, regs->SR1 ) )
849  // Buss Error When Master Only
850  || ((BIT_X_IS_SET_IN_REG( I2C_SR1_BIT_ERR_BUS, regs->SR1 ) ) && (!BIT_X_IS_SET_IN_REG( I2C_SR2_BIT_MSL, regs->SR2 ) ))
851  || (BIT_X_IS_SET_IN_REG( I2C_SR1_BIT_ERR_OVR, regs->SR1 ) )
852  )
853  {
854  ret = STMI2C_SubTra_Error;
855  }
856 */
857 
858  // Count The Errors
859  i2c_error(periph);
860 
861  // Clear Running Events
863 
864  }
865 
866 
868  // Normal Event:
869  else
870  {
871 
872  if (trans->type == I2CTransRx) // TxRx are converted to Rx after the Tx Part
873  {
874  switch (trans->len_r)
875  {
876  case 1:
877  ret = stmi2c_read1(regs,trans);
878  break;
879  case 2:
880  ret = stmi2c_read2(regs,trans);
881  break;
882  default:
883  ret = stmi2c_readmany(regs,periph, trans);
884  break;
885  }
886  }
887  else // TxRx or Tx
888  {
889  ret = stmi2c_send(regs,periph,trans);
890  }
891  }
892 
894  // Sub-transaction has finished
895  if (ret != STMI2C_SubTra_Busy)
896  {
897  // If a restart is not needed
898  if (trans->type != I2CTransTxRx)
899  {
900  // Ready, no stop condition set yet
901  if (ret == STMI2C_SubTra_Ready)
902  {
903 
904  // Program a stop
905  PPRZ_I2C_SEND_STOP(regs);
906 
907  // Silent any BTF that would occur before STOP is executed
908  regs->DR = 0x00;
909  }
910 
911  // In case of unexpected condition: e.g. not slave, no event
912  if (ret == STMI2C_SubTra_Error)
913  {
914 
915  trans->status = I2CTransFailed;
916 
917  // Error
918 #ifdef I2C_DEBUG_LED
919  LED2_ON();
920  LED1_ON();
921  LED2_OFF();
922  LED1_OFF();
923 #endif
924 
925  LED_SHOW_ACTIVE_BITS(regs);
926 
927  // Clear Running Events
929 
930  }
931 
932 
933  // Jump to the next transaction
934  periph->trans_extract_idx++;
936  periph->trans_extract_idx = 0;
937 
938  // Tell everyone we are ready
939  periph->status = I2CIdle;
940 
941 
942  // if we have no more transaction to process, stop here
943  if (periph->trans_extract_idx == periph->trans_insert_idx)
944  {
945 
946 #ifdef I2C_DEBUG_LED
947  LED2_ON();
948  LED1_ON();
949  LED1_OFF();
950  LED1_ON();
951  LED1_OFF();
952  LED2_OFF();
953 #endif
954  }
955  // if not, start next transaction
956  else
957  {
958  // Restart transaction doing the Rx part now
959 // --- moved to idle function
960  PPRZ_I2C_SEND_START(periph);
961 // ------
962  }
963 
964  }
965  // RxTx -> Restart and do Rx part
966  else
967  {
968  trans->type = I2CTransRx;
969  periph->status = I2CStartRequested;
970  regs->CR1 |= I2C_CR1_BIT_START;
971 
972  // Silent any BTF that would occur before SB
973  regs->DR = 0x00;
974  }
975  }
976 
977  return;
978 }
979 
980 static inline void i2c_error(struct i2c_periph *periph)
981 {
982  uint8_t err_nr = 0;
983  periph->errors->er_irq_cnt;
984  if (I2C_GetITStatus(periph->reg_addr, I2C_IT_AF)) { /* Acknowledge failure */
985  periph->errors->ack_fail_cnt++;
986  I2C_ClearITPendingBit(periph->reg_addr, I2C_IT_AF);
987  err_nr = 1;
988  }
989  if (I2C_GetITStatus(periph->reg_addr, I2C_IT_BERR)) { /* Misplaced Start or Stop condition */
990  periph->errors->miss_start_stop_cnt++;
991  I2C_ClearITPendingBit(periph->reg_addr, I2C_IT_BERR);
992  err_nr = 2;
993  }
994  if (I2C_GetITStatus(periph->reg_addr, I2C_IT_ARLO)) { /* Arbitration lost */
995  periph->errors->arb_lost_cnt++;
996  I2C_ClearITPendingBit(periph->reg_addr, I2C_IT_ARLO);
997  err_nr = 3;
998  }
999  if (I2C_GetITStatus(periph->reg_addr, I2C_IT_OVR)) { /* Overrun/Underrun */
1000  periph->errors->over_under_cnt++;
1001  I2C_ClearITPendingBit(periph->reg_addr, I2C_IT_OVR);
1002  err_nr = 4;
1003  }
1004  if (I2C_GetITStatus(periph->reg_addr, I2C_IT_PECERR)) { /* PEC Error in reception */
1005  periph->errors->pec_recep_cnt++;
1006  I2C_ClearITPendingBit(periph->reg_addr, I2C_IT_PECERR);
1007  err_nr = 5;
1008  }
1009  if (I2C_GetITStatus(periph->reg_addr, I2C_IT_TIMEOUT)) { /* Timeout or Tlow error */
1010  periph->errors->timeout_tlow_cnt++;
1011  I2C_ClearITPendingBit(periph->reg_addr, I2C_IT_TIMEOUT);
1012  err_nr = 6;
1013  }
1014  if (I2C_GetITStatus(periph->reg_addr, I2C_IT_SMBALERT)) { /* SMBus alert */
1015  periph->errors->smbus_alert_cnt++;
1016  I2C_ClearITPendingBit(periph->reg_addr, I2C_IT_SMBALERT);
1017  err_nr = 7;
1018  }
1019 
1020 #ifdef I2C_DEBUG_LED
1021  LED_ERROR(20, err_nr);
1022 #endif
1023 
1024  return;
1025 
1026 }
1027 
1028 
1029 /*
1030  // Make sure the bus is free before resetting (p722)
1031  if (regs->SR2 & (I2C_FLAG_BUSY >> 16)) {
1032  // Reset the I2C block
1033  I2C_SoftwareResetCmd(periph->reg_addr, ENABLE);
1034  I2C_SoftwareResetCmd(periph->reg_addr, DISABLE);
1035  }
1036 */
1037 
1038 //#endif /* USE_I2C2 */
1039 
1040 
1041 
1042 
1043 #ifdef USE_I2C1
1044 
1045 struct i2c_errors i2c1_errors;
1046 
1047 void i2c1_hw_init(void) {
1048 
1049  i2c1.reg_addr = I2C1;
1050  i2c1.init_struct = &I2C1_InitStruct;
1051  i2c1.scl_pin = GPIO_Pin_6;
1052  i2c1.sda_pin = GPIO_Pin_7;
1053  i2c1.errors = &i2c1_errors;
1054 
1055  /* zeros error counter */
1056  ZEROS_ERR_COUNTER(i2c1_errors);
1057 
1058  // Extra
1059 #ifdef I2C_DEBUG_LED
1060  LED_INIT();
1061 #else
1062 
1063  /* reset peripheral to default state ( sometimes not achieved on reset :( ) */
1064  //I2C_DeInit(I2C1);
1065 
1066  NVIC_PriorityGroupConfig(NVIC_PriorityGroup_0);
1067  NVIC_InitTypeDef NVIC_InitStructure;
1068 
1069  /* Configure and enable I2C1 event interrupt --------------------------------*/
1070  NVIC_InitStructure.NVIC_IRQChannel = I2C1_EV_IRQn;
1071  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
1072  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
1073  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
1074  NVIC_Init(&NVIC_InitStructure);
1075 
1076  /* Configure and enable I2C1 err interrupt ----------------------------------*/
1077  NVIC_InitStructure.NVIC_IRQChannel = I2C1_ER_IRQn;
1078  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
1079  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
1080  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
1081  NVIC_Init(&NVIC_InitStructure);
1082 
1083  /* Enable peripheral clocks -------------------------------------------------*/
1084  /* Enable I2C1 clock */
1085  RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2C1, ENABLE);
1086  /* Enable GPIOB clock */
1087  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
1088 
1089  GPIO_InitTypeDef GPIO_InitStructure;
1090  GPIO_InitStructure.GPIO_Pin = i2c1.scl_pin | i2c1.sda_pin;
1091  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
1092  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
1093  GPIO_Init(GPIOB, &GPIO_InitStructure);
1094 
1095  I2C_DeInit(I2C1);
1096 
1097  // enable peripheral
1098  I2C_Cmd(I2C1, ENABLE);
1099 
1100  I2C_Init(I2C1, i2c1.init_struct);
1101 
1102  // enable error interrupts
1103  I2C_ITConfig(I2C1, I2C_IT_ERR, ENABLE);
1104 
1105 #endif
1106 }
1107 
1108 void i2c1_ev_irq_handler(void) {
1109  i2c_irq(&i2c1);
1110 }
1111 
1112 void i2c1_er_irq_handler(void) {
1113  i2c_irq(&i2c1);
1114 }
1115 
1116 #endif /* USE_I2C1 */
1117 
1118 #ifdef USE_I2C2
1119 
1120 struct i2c_errors i2c2_errors;
1121 
1122 void i2c2_hw_init(void) {
1123 
1124  i2c2.reg_addr = I2C2;
1125  i2c2.init_struct = &I2C2_InitStruct;
1126  i2c2.scl_pin = GPIO_Pin_10;
1127  i2c2.sda_pin = GPIO_Pin_11;
1128  i2c2.errors = &i2c2_errors;
1129 
1130  /* zeros error counter */
1131  ZEROS_ERR_COUNTER(i2c2_errors);
1132 
1133  /* reset peripheral to default state ( sometimes not achieved on reset :( ) */
1134  //I2C_DeInit(I2C2);
1135 
1136  NVIC_PriorityGroupConfig(NVIC_PriorityGroup_0);
1137  NVIC_InitTypeDef NVIC_InitStructure;
1138 
1139  /* Configure and enable I2C2 event interrupt --------------------------------*/
1140  NVIC_InitStructure.NVIC_IRQChannel = I2C2_EV_IRQn;
1141  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
1142  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
1143  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
1144  NVIC_Init(&NVIC_InitStructure);
1145 
1146  /* Configure and enable I2C2 err interrupt ----------------------------------*/
1147  NVIC_InitStructure.NVIC_IRQChannel = I2C2_ER_IRQn;
1148  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
1149  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
1150  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
1151  NVIC_Init(&NVIC_InitStructure);
1152 
1153  /* Enable peripheral clocks -------------------------------------------------*/
1154  /* Enable I2C2 clock */
1155  RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2C2, ENABLE);
1156  /* Enable GPIOB clock */
1157  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
1158 
1159  GPIO_InitTypeDef GPIO_InitStructure;
1160  GPIO_InitStructure.GPIO_Pin = i2c2.scl_pin | i2c2.sda_pin;
1161  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
1162  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
1163  GPIO_Init(GPIOB, &GPIO_InitStructure);
1164 
1165  I2C_DeInit(I2C2);
1166 
1167  // enable peripheral
1168  I2C_Cmd(I2C2, ENABLE);
1169 
1170  I2C_Init(I2C2, i2c2.init_struct);
1171 
1172  // enable error interrupts
1173  I2C_ITConfig(I2C2, I2C_IT_ERR, ENABLE);
1174 
1175 }
1176 
1177 
1178 
1179 void i2c2_ev_irq_handler(void) {
1180  i2c_irq(&i2c2);
1181 }
1182 
1183 void i2c2_er_irq_handler(void) {
1184  i2c_irq(&i2c2);
1185 }
1186 
1187 #endif /* USE_I2C2 */
1188 
1189 
1190 void i2c_setbitrate(struct i2c_periph *periph, int bitrate)
1191 {
1192  if (i2c_idle(periph))
1193  {
1194  if (periph == &i2c2)
1195  {
1196  I2C2_InitStruct.I2C_ClockSpeed = bitrate;
1197  I2C_Init(I2C2, i2c2.init_struct);
1198  }
1199 
1200 #ifdef I2C_DEBUG_LED
1201  __disable_irq();
1202 
1203  LED2_ON();
1204  LED1_ON();
1205  LED2_OFF();
1206  LED1_OFF();
1207  LED2_ON();
1208  LED1_ON();
1209  LED2_OFF();
1210  LED1_OFF();
1211 
1212  __enable_irq();
1213 #endif
1214 
1215  }
1216 }
1217 
1218 void i2c_event(void)
1219 {
1220  static uint32_t cnt = 0;
1221  //I2C_TypeDef *regs;
1222  cnt++;
1223  if (cnt > 10000) cnt = 0;
1224 
1225 #ifndef I2C_DEBUG_LED
1226 #ifdef USE_I2C1
1227  if (i2c1.status == I2CIdle)
1228  {
1229  if (i2c_idle(&i2c1))
1230  {
1231  __disable_irq();
1232  // More work to do
1233  if (i2c1.trans_extract_idx != i2c1.trans_insert_idx)
1234  {
1235  // Restart transaction doing the Rx part now
1236  PPRZ_I2C_SEND_START(&i2c1);
1237  }
1238  __enable_irq();
1239  }
1240  }
1241 #endif
1242 #endif
1243 
1244 #ifdef USE_I2C2
1245 
1246 #ifdef I2C_DEBUG_LED
1247  if (cnt == 0)
1248  {
1249  __disable_irq();
1250 
1251  LED2_ON();
1252  LED1_ON();
1253  LED1_OFF();
1254  LED1_ON();
1255  LED1_OFF();
1256  LED1_ON();
1257  LED1_OFF();
1258  LED1_ON();
1259  LED1_OFF();
1260  if (i2c2.status == I2CIdle)
1261  {
1262  LED1_ON();
1263  LED1_OFF();
1264  }
1265  else if (i2c2.status == I2CStartRequested)
1266  {
1267  LED1_ON();
1268  LED1_OFF();
1269  LED1_ON();
1270  LED1_OFF();
1271 
1272  }
1273  LED2_OFF();
1274 
1275  //regs = (I2C_TypeDef *) i2c2.reg_addr;
1276  //LED_SHOW_ACTIVE_BITS(regs);
1277 
1278  __enable_irq();
1279  }
1280 #endif
1281 
1282 
1283  //if (i2c2.status == I2CIdle)
1284  {
1285  //if (i2c_idle(&i2c2))
1286  {
1287  //__disable_irq();
1288  // More work to do
1289  //if (i2c2.trans_extract_idx != i2c2.trans_insert_idx)
1290  {
1291  // Restart transaction doing the Rx part now
1292  //PPRZ_I2C_SEND_START(&i2c2);
1293  }
1294  //__enable_irq();
1295  }
1296  }
1297 #endif
1298 }
1299 
1301 // Implement Interface Functions
1302 
1303 bool_t i2c_submit(struct i2c_periph* periph, struct i2c_transaction* t) {
1304 
1305  uint8_t temp;
1306  temp = periph->trans_insert_idx + 1;
1307  if (temp >= I2C_TRANSACTION_QUEUE_LEN) temp = 0;
1308  if (temp == periph->trans_extract_idx)
1309  return FALSE; // queue full
1310 
1311  t->status = I2CTransPending;
1312 
1313  __disable_irq();
1314  /* put transacation in queue */
1315  periph->trans[periph->trans_insert_idx] = t;
1316  periph->trans_insert_idx = temp;
1317 
1318  /* if peripheral is idle, start the transaction */
1319  // if (PPRZ_I2C_IS_IDLE(p))
1320  if (periph->status == I2CIdle)
1321  {
1322  //if (i2c_idle(periph))
1323  {
1324 #ifdef I2C_DEBUG_LED
1325  if (periph == &i2c1)
1326  {
1327 
1328  }
1329  else
1330 #endif
1331  {
1332  PPRZ_I2C_SEND_START(periph);
1333  }
1334  }
1335  }
1336  /* else it will be started by the interrupt handler when the previous transactions completes */
1337  __enable_irq();
1338 
1339  return TRUE;
1340 }
1341 
1342 bool_t i2c_idle(struct i2c_periph* periph)
1343 {
1344  I2C_TypeDef *regs = (I2C_TypeDef *) periph->reg_addr;
1345 
1346 #ifdef I2C_DEBUG_LED
1347  if (periph == &i2c1)
1348  {
1349  return TRUE;
1350  }
1351 #endif
1352  if (periph->status == I2CIdle)
1353  return ! (BIT_X_IS_SET_IN_REG( I2C_SR2_BIT_BUSY, regs->SR2 ) );
1354  else
1355  return FALSE;
1356 }
1357 
1358 
#define I2C_CR2_BIT_ITERREN
unsigned short uint16_t
Definition: types.h:16
static void LED_SHOW_ACTIVE_BITS(I2C_TypeDef *regs)
#define I2C_SR1_BIT_BTF
#define I2C1
Definition: LPC21xx.h:166
#define I2C_SR1_BITS_ERR
#define I2C_SR2_BIT_TRA
#define I2C_DEBUG_LED
#define I2C_CR1_BIT_ACK
static enum STMI2CSubTransactionStatus stmi2c_readmany(I2C_TypeDef *regs, struct i2c_periph *periph, struct i2c_transaction *trans)
void * reg_addr
Definition: i2c.h:62
uint8_t trans_extract_idx
Definition: i2c.h:58
volatile uint16_t ack_fail_cnt
Definition: i2c.h:71
bool_t i2c_submit(struct i2c_periph *periph, struct i2c_transaction *t)
static void stmi2c_clear_pending_interrupts(I2C_TypeDef *regs)
#define __I2C_REG_CRITICAL_ZONE_STOP
static enum STMI2CSubTransactionStatus stmi2c_send(I2C_TypeDef *regs, struct i2c_periph *periph, struct i2c_transaction *trans)
#define I2C_SR1_BIT_ADDR
#define __I2C_REG_CRITICAL_ZONE_START
static void i2c_irq(struct i2c_periph *periph)
#define I2C_SR2_BIT_MSL
volatile uint8_t idx_buf
Definition: i2c.h:61
enum I2CStatus status
Definition: i2c.h:60
uint8_t slave_addr
Definition: i2c.h:43
#define FALSE
Definition: imu_chimu.h:141
volatile uint16_t smbus_alert_cnt
Definition: i2c.h:77
volatile uint16_t timeout_tlow_cnt
Definition: i2c.h:76
#define I2C_CR1_BIT_PE
Definition: i2c.h:23
static void PPRZ_I2C_SEND_STOP(I2C_TypeDef *regs)
static void PPRZ_I2C_SEND_START(struct i2c_periph *periph)
#define I2C_CR1_BIT_SWRST
volatile uint16_t miss_start_stop_cnt
Definition: i2c.h:72
#define I2C_CR1_BIT_START
unsigned long uint32_t
Definition: types.h:18
static void LED2_ON(void)
#define I2C_CR2_BIT_ITBUFEN
volatile uint16_t unexpected_event_cnt
Definition: i2c.h:78
#define I2C_SR2_BIT_BUSY
Definition: i2c.h:70
enum I2CTransactionStatus status
Definition: i2c.h:47
#define I2C_SR1_BIT_SB
volatile uint16_t over_under_cnt
Definition: i2c.h:74
static void LED2_OFF(void)
volatile uint16_t pec_recep_cnt
Definition: i2c.h:75
void i2c_setbitrate(struct i2c_periph *periph, int bitrate)
void i2c_event(void)
#define TRUE
Definition: imu_chimu.h:144
volatile uint32_t er_irq_cnt
Definition: i2c.h:80
volatile uint8_t buf[I2C_BUF_LEN]
Definition: i2c.h:46
STMI2CSubTransactionStatus
static enum STMI2CSubTransactionStatus stmi2c_read1(I2C_TypeDef *regs, struct i2c_transaction *trans)
uint8_t len_w
Definition: i2c.h:45
uint16_t len_r
Definition: i2c.h:44
#define I2C_CR1_BIT_POS
static void LED1_OFF(void)
unsigned char uint8_t
Definition: types.h:14
volatile uint16_t arb_lost_cnt
Definition: i2c.h:73
#define I2C_CR1_BIT_STOP
uint8_t trans_insert_idx
Definition: i2c.h:57
#define ZEROS_ERR_COUNTER(_i2c_err)
Definition: i2c.h:94
#define I2C_SR1_BIT_TXE
struct i2c_errors * errors
Definition: i2c.h:66
Definition: i2c.h:54
enum I2CTransactionType type
Definition: i2c.h:42
static void LED_ERROR(uint8_t base, uint8_t nr)
#define I2C_SR1_BIT_RXNE
Definition: i2c.h:10
static void LED_INIT(void)
#define I2C_TRANSACTION_QUEUE_LEN
Definition: i2c.h:51
#define I2C_CR2_BIT_ITEVTEN
static void LED1_ON(void)
bool_t i2c_idle(struct i2c_periph *periph)
Definition: i2c.h:9
#define BIT_X_IS_SET_IN_REG(X, REG)
__attribute__((always_inline))
Definition: i2c_arch.c:35
static void i2c_error(struct i2c_periph *periph)
static enum STMI2CSubTransactionStatus stmi2c_read2(I2C_TypeDef *regs, struct i2c_transaction *trans)
struct i2c_transaction * trans[I2C_TRANSACTION_QUEUE_LEN]
Definition: i2c.h:56