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i2c_attempt3_subtra.c
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1 #include "mcu_periph/i2c.h"
2 
3 #include <stm32/rcc.h>
4 #include <stm32/gpio.h>
5 #include <stm32/flash.h>
6 #include <stm32/misc.h>
7 
8 #define I2C_DEBUG_LED
9 
11 // TODO: remove this
12 
13 
14 #ifdef I2C_DEBUG_LED
15 
16 static inline void LED1_ON(void)
17 {
18  GPIO_WriteBit(GPIOB, GPIO_Pin_6 , Bit_SET );
19 }
20 
21 static inline void LED1_OFF(void)
22 {
23  GPIO_WriteBit(GPIOB, GPIO_Pin_6 , !Bit_SET );
24 }
25 
26 static inline void LED2_ON(void)
27 {
28  GPIO_WriteBit(GPIOB, GPIO_Pin_7 , Bit_SET );
29 }
30 
31 static inline void LED2_OFF(void)
32 {
33  GPIO_WriteBit(GPIOB, GPIO_Pin_7 , !Bit_SET );
34 }
35 
36 static inline void LED_INIT(void)
37 {
38  GPIO_InitTypeDef GPIO_InitStructure;
39  RCC_APB2PeriphClockCmd( RCC_APB2Periph_GPIOB, ENABLE);
40  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_6;
41  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
42  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
43  GPIO_Init(GPIOB, &GPIO_InitStructure);
44 
45  LED1_OFF();
46  LED2_OFF();
47 }
48 
49 
50 static inline void LED_ERROR(uint8_t base, uint8_t nr)
51 {
52  LED2_ON();
53  for (int i=0;i<(base+nr);i++)
54  {
55  LED1_ON();
56  LED1_OFF();
57  }
58  LED2_OFF();
59 }
60 #endif
61 
64 
65 #ifdef USE_I2C1
66 static I2C_InitTypeDef I2C1_InitStruct = {
67  .I2C_Mode = I2C_Mode_I2C,
68  .I2C_DutyCycle = I2C_DutyCycle_2,
69  .I2C_OwnAddress1 = 0x00,
70  .I2C_Ack = I2C_Ack_Enable,
71  .I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit,
72  .I2C_ClockSpeed = 40000
73 };
74 #endif
75 
76 #ifdef USE_I2C2
77 static I2C_InitTypeDef I2C2_InitStruct = {
78  .I2C_Mode = I2C_Mode_I2C,
79  .I2C_DutyCycle = I2C_DutyCycle_2,
80  .I2C_OwnAddress1 = 0x00,
81  .I2C_Ack = I2C_Ack_Enable,
82  .I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit,
83 // .I2C_ClockSpeed = 37000
84  .I2C_ClockSpeed = 400000
85 };
86 #endif
87 
90 
91 // Bypassing the libSTM I2C functions to have more control over the reading of registers
92 // e.g. SR1 and SR2 should not always be read together as it might unwantedly clear ADDR flags etc.
93 
94 // Referring to STM32 manual:
95 // -Doc ID 13902 Rev 11
96 
97 // Status Register 1
98 
99 #define I2C_SR1_BIT_SB (1<<0) // Start Condition Met
100 #define I2C_SR1_BIT_ADDR (1<<1) // Address Sent
101 #define I2C_SR1_BIT_BTF (1<<2) // SCL held low
102 #define I2C_SR1_BIT_RXNE (1<<6) // Data Read Available
103 #define I2C_SR1_BIT_TXE (1<<7) // TX buffer space available
104 
105 #define I2C_SR1_BIT_ERR_BUS (1<<8) // Misplaced Start/Stop (usually interference)
106 #define I2C_SR1_BIT_ERR_ARLO (1<<9) // Arbitration Lost (in multimaster) or SDA short-to-ground (in single master)
107 #define I2C_SR1_BIT_ERR_AF (1<<10) // Ack Failure (too fast/too soon/no sensor/wiring break/...)
108 #define I2C_SR1_BIT_ERR_OVR (1<<11) // Overrun [data loss] (in slave) or SCL short-to-ground (in single master)
109 
110 #define I2C_SR1_BITS_ERR ((1<<8)|(1<<9)|(1<<10)|(1<<11)|(1<<12)|(1<<14)|(1<<15))
111 
112 // Status Register 2
113 
114 #define I2C_SR2_BIT_TRA (1<<2) // Transmitting
115 #define I2C_SR2_BIT_BUSY (1<<1) // Busy
116 #define I2C_SR2_BIT_MSL (1<<0) // Master Selected
117 
118 // Control Register 1
119 
120 #define I2C_CR1_BIT_PE (1<<0) // Peripheral Enable
121 #define I2C_CR1_BIT_START (1<<8) // Generate a Start
122 #define I2C_CR1_BIT_STOP (1<<9) // Generate a Stop
123 #define I2C_CR1_BIT_ACK (1<<10) // ACK / NACK
124 #define I2C_CR1_BIT_POS (1<<11) // Ack will control not the next but secondnext received byte
125 #define I2C_CR1_BIT_SWRST (1<<15) // Clear Busy Condition when no stop was detected
126 
127 // Control Register 2
128 
129 #define I2C_CR2_BIT_ITERREN (1<<8) // Error Interrupt
130 #define I2C_CR2_BIT_ITEVTEN (1<<9) // Event Interrupt
131 #define I2C_CR2_BIT_ITBUFEN (1<<10) // Buffer Interrupt
132 
133 
134 // Bit Control
135 
136 #define BIT_X_IS_SET_IN_REG(X,REG) (((REG) & (X)) == (X))
137 
140 
141 // TODO: remove debug
142 #ifdef I2C_DEBUG_LED
143 
144 static inline void LED_SHOW_ACTIVE_BITS(I2C_TypeDef *regs)
145 {
146  uint16_t CR1 = regs->CR1;
147  uint16_t SR1 = regs->SR1;
148  uint16_t SR2 = regs->SR2;
149  // Note: reading SR1 and then SR2 will clear ADDR bits
150 
151  LED1_ON();
152 
153  // 1 Start
154  if (BIT_X_IS_SET_IN_REG( I2C_SR1_BIT_SB, SR1 ) )
155  LED2_ON();
156  else
157  LED2_OFF();
158  LED2_OFF();
159 
160  // 2 Addr
162  LED2_ON();
163  else
164  LED2_OFF();
165  LED2_OFF();
166 
167  // 3 BTF
169  LED2_ON();
170  else
171  LED2_OFF();
172  LED2_OFF();
173 
174  // 4 ERROR
175  if (( SR1 & I2C_SR1_BITS_ERR ) != 0x0000)
176  LED2_ON();
177  else
178  LED2_OFF();
179  LED2_OFF();
180 
181  // Anything?
182  if (( SR1 + SR2) != 0x0000)
183  LED2_ON();
184  else
185  LED2_OFF();
186  LED2_OFF();
187 
188  LED1_OFF();
189 
190 
191  LED1_ON();
192 
193  // 1 Start
195  LED2_ON();
196  else
197  LED2_OFF();
198  LED2_OFF();
199 
200  // 2 Stop
202  LED2_ON();
203  else
204  LED2_OFF();
205  LED2_OFF();
206 
207  // 3 Busy
209  LED2_ON();
210  else
211  LED2_OFF();
212  LED2_OFF();
213 
214  // 4 Tra
216  LED2_ON();
217  else
218  LED2_OFF();
219  LED2_OFF();
220 
221  // 5 Master
223  LED2_ON();
224  else
225  LED2_OFF();
226  LED2_OFF();
227  LED1_OFF();
228 
229  LED1_ON();
230 
231  // 1 Anything CR?
232  if (( CR1) != 0x0000)
233  LED2_ON();
234  else
235  LED2_OFF();
236  LED2_OFF();
237 
238  // 2 PE
239  if (BIT_X_IS_SET_IN_REG( I2C_CR1_BIT_PE, CR1 ) )
240  LED2_ON();
241  else
242  LED2_OFF();
243  LED2_OFF();
244 
245  // 3 SWRESET
247  LED2_ON();
248  else
249  LED2_OFF();
250  LED2_OFF();
251 
252  LED1_OFF();
253 
254 }
255 #endif
256 
257 static inline void PPRZ_I2C_SEND_STOP(I2C_TypeDef *regs)
258 {
259  // Man: p722: Stop generation after the current byte transfer or after the current Start condition is sent.
260  regs->CR1 |= I2C_CR1_BIT_STOP;
261 
262 #ifdef I2C_DEBUG_LED
263  LED2_ON();
264  LED1_ON();
265  LED1_OFF();
266  LED2_OFF();
267 #endif
268 }
269 
270 // (RE)START
271 
272 static inline void PPRZ_I2C_SEND_START(struct i2c_periph *periph)
273 {
274  I2C_TypeDef *regs = (I2C_TypeDef *) periph->reg_addr;
275 
276  periph->idx_buf = 0;
277 
278 #ifdef I2C_DEBUG_LED
279  LED_SHOW_ACTIVE_BITS(regs);
280 
281  LED2_ON();
282  LED1_ON();
283  LED1_OFF();
284  LED1_ON();
285  LED1_OFF();
286  LED1_ON();
287  LED1_OFF();
288  LED2_OFF();
289 
290 #endif
291 
292 /*
293  if (BIT_X_IS_SET_IN_REG( I2C_CR1_BIT_STOP, regs->CR1 ) )
294  {
295  regs->CR1 &= ~ I2C_CR1_BIT_STOP;
296  }
297 */
298 
299  // Enable Error IRQ, Event IRQ but disable Buffer IRQ
300  regs->CR2 |= I2C_CR2_BIT_ITERREN;
301  regs->CR2 |= I2C_CR2_BIT_ITEVTEN;
302  regs->CR2 &= ~ I2C_CR2_BIT_ITBUFEN;
303 
304  // Issue a new start
305  regs->CR1 = (I2C_CR1_BIT_START | I2C_CR1_BIT_PE);
306  periph->status = I2CStartRequested;
307 
308 
309 #ifdef I2C_DEBUG_LED
310  LED_SHOW_ACTIVE_BITS(regs);
311 #endif
312 }
313 
314 // STOP
315 
318 //
319 // SUBTRANSACTION SEQUENCES
320 
325 };
326 
327 static inline enum STMI2CSubTransactionStatus stmi2c_send(I2C_TypeDef *regs, struct i2c_periph *periph, struct i2c_transaction *trans)
328 {
329  uint16_t SR1 = regs->SR1;
330 
331  // Start Condition Was Just Generated
332  if (BIT_X_IS_SET_IN_REG( I2C_SR1_BIT_SB, SR1 ) )
333  {
334  // Disable buffer interrupt
335  regs->CR2 &= ~ I2C_CR2_BIT_ITBUFEN;
336  // Send Slave address and wait for ADDR interrupt
337  regs->DR = trans->slave_addr;
338  }
339  // Address Was Sent
340  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BIT_ADDR, SR1) )
341  {
342  // Now read SR2 to clear the ADDR
343  uint16_t SR2 __attribute__ ((unused)) = regs->SR2;
344 
345  // Maybe check we are transmitting (did not loose arbitration for instance)
346  // if (! BIT_X_IS_SET_IN_REG(I2C_SR2_BIT_TRA, SR2)) { }
347 
348  // Send First max 2 bytes
349  regs->DR = trans->buf[0];
350  if (trans->len_w > 1)
351  {
352  regs->DR = trans->buf[1];
353  periph->idx_buf = 2;
354  }
355  else
356  {
357  periph->idx_buf = 1;
358  }
359 
360  // Enable buffer-space available interrupt
361  // only if there is more to send: wait for TXE, no more to send: wait for BTF
362  if ( periph->idx_buf < trans->len_w)
363  regs->CR2 |= I2C_CR2_BIT_ITBUFEN;
364  }
365  // The buffer is not full anymore AND we were not waiting for BTF
367  {
368  // Send the next byte
369  regs->DR = trans->buf[periph->idx_buf];
370  periph->idx_buf++;
371 
372  // All bytes Sent? Then wait for BTF instead
373  if ( periph->idx_buf >= trans->len_w)
374  {
375  // Not interested anymore to know the buffer has space left
376  regs->CR2 &= ~ I2C_CR2_BIT_ITBUFEN;
377  // Next interrupt will be BTF (or error)
378  }
379  }
380  // BTF: means last byte was sent
381  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BIT_BTF, SR1) )
382  {
383  if (trans->type == I2CTransTx)
384  {
385  // Tell the driver we are ready
386  trans->status = I2CTransSuccess;
387  }
388 
389  return STMI2C_SubTra_Ready;
390  }
391 
392  return STMI2C_SubTra_Busy;
393 }
394 
395 static inline enum STMI2CSubTransactionStatus stmi2c_read1(I2C_TypeDef *regs, struct i2c_transaction *trans)
396 {
397  uint16_t SR1 = regs->SR1;
398 
399  // Start Condition Was Just Generated
400  if (BIT_X_IS_SET_IN_REG( I2C_SR1_BIT_SB, SR1 ) )
401  {
402  regs->CR2 &= ~ I2C_CR2_BIT_ITBUFEN;
403  regs->DR = trans->slave_addr | 0x01;
404  }
405  // Address Was Sent
406  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BIT_ADDR, SR1) )
407  {
408  // First Clear the ACK bit: after the next byte we do not want new bytes
409  regs->CR1 &= ~ I2C_CR1_BIT_POS;
410  regs->CR1 &= ~ I2C_CR1_BIT_ACK;
411 
412  // --- next to steps MUST be executed together to avoid missing the stop
413  __disable_irq();
414 
415  // Only after setting ACK, read SR2 to clear the ADDR (next byte will start arriving)
416  uint16_t SR2 __attribute__ ((unused)) = regs->SR2;
417 
418  // Schedule a Stop
419  PPRZ_I2C_SEND_STOP(regs);
420 
421  __enable_irq();
422  // --- end of critical zone -----------
423 
424  // Enable the RXNE to get the result
425  regs->CR2 |= I2C_CR2_BIT_ITBUFEN;
426  }
427  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BIT_RXNE, SR1) )
428  {
429  regs->CR2 &= ~ I2C_CR2_BIT_ITBUFEN;
430  trans->buf[0] = regs->DR;
431 
432  // We got all the results (stop condition might still be in progress but this is the last interrupt)
433  trans->status = I2CTransSuccess;
434 
436  }
437 
438  return STMI2C_SubTra_Busy;
439 }
440 
441 static inline enum STMI2CSubTransactionStatus stmi2c_read2(I2C_TypeDef *regs, struct i2c_transaction *trans)
442 {
443  uint16_t SR1 = regs->SR1;
444 
445  // Start Condition Was Just Generated
446  if (BIT_X_IS_SET_IN_REG( I2C_SR1_BIT_SB, SR1 ) )
447  {
448  regs->CR2 &= ~ I2C_CR2_BIT_ITBUFEN;
449  regs->CR1 |= I2C_CR1_BIT_ACK;
450  regs->CR1 |= I2C_CR1_BIT_POS;
451  regs->DR = trans->slave_addr | 0x01;
452  }
453  // Address Was Sent
454  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BIT_ADDR, SR1) )
455  {
456  // BEFORE clearing ACK, read SR2 to clear the ADDR (next byte will start arriving)
457  // clearing ACK after the byte transfer has already started will NACK the next (2nd)
458  uint16_t SR2 __attribute__ ((unused)) = regs->SR2;
459 
460  // --- make absolutely sure this command is not delayed too much after the previous:
461  __disable_irq();
462  // if transfer of DR was finished already then we will get too many bytes
463  // NOT First Clear the ACK bit but only AFTER clearing ADDR
464  regs->CR1 &= ~ I2C_CR1_BIT_ACK;
465 
466  // Disable the RXNE and wait for BTF
467  regs->CR2 &= ~ I2C_CR2_BIT_ITBUFEN;
468 
469  __enable_irq();
470  // --- end of critical zone -----------
471  }
472  // Receive buffer if full, master is halted: BTF
473  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BIT_BTF, SR1) )
474  {
475  // Stop condition MUST be set BEFORE reading the DR
476  // otherwise since there is new buffer space a new byte will be read
477  PPRZ_I2C_SEND_STOP(regs);
478 
479  trans->buf[0] = regs->DR;
480  trans->buf[1] = regs->DR;
481 
482  // We got all the results
483  trans->status = I2CTransSuccess;
484 
486  }
487 
488  return STMI2C_SubTra_Busy;
489 }
490 
491 static inline enum STMI2CSubTransactionStatus stmi2c_readmany(I2C_TypeDef *regs, struct i2c_periph *periph, struct i2c_transaction *trans)
492 {
493  uint16_t SR1 = regs->SR1;
494 
495  // Start Condition Was Just Generated
496  if (BIT_X_IS_SET_IN_REG( I2C_SR1_BIT_SB, SR1 ) )
497  {
498  regs->CR2 &= ~ I2C_CR2_BIT_ITBUFEN;
499  // The first data byte will be acked in read many so the slave knows it should send more
500  regs->CR1 &= ~ I2C_CR1_BIT_POS;
501  regs->CR1 |= I2C_CR1_BIT_ACK;
502  // Clear the SB flag
503  regs->DR = trans->slave_addr | 0x01;
504  }
505  // Address Was Sent
506  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BIT_ADDR, SR1) )
507  {
508  periph->idx_buf = 0;
509 
510  // Enable RXNE: receive an interrupt any time a byte is available
511  // only enable if MORE than 3 bytes need to be read
512  if (periph->idx_buf < (trans->len_r - 3))
513  {
514  regs->CR2 |= I2C_CR2_BIT_ITBUFEN;
515  }
516 
517  // ACK is still on to get more DATA
518  // Read SR2 to clear the ADDR (next byte will start arriving)
519  uint16_t SR2 __attribute__ ((unused)) = regs->SR2;
520  }
521  // one or more bytes are available AND we were interested in Buffer interrupts
523  {
524  // read byte until 3 bytes remain to be read (e.g. len_r = 6, -> idx=3 means idx 3,4,5 = 3 remain to be read
525  if (periph->idx_buf < (trans->len_r - 3))
526  {
527  trans->buf[periph->idx_buf] = regs->DR;
528  periph->idx_buf ++;
529  }
530  // from : 3bytes -> last byte: do nothing
531  //
532  // finally: this was the last byte
533  else if (periph->idx_buf >= (trans->len_r - 1))
534  {
535  regs->CR2 &= ~ I2C_CR2_BIT_ITBUFEN;
536 
537  // Last Value
538  trans->buf[periph->idx_buf] = regs->DR;
539  periph->idx_buf ++;
540 
541  // We got all the results
542  trans->status = I2CTransSuccess;
543 
545  }
546 
547  // Check for end of transaction: start waiting for BTF instead of RXNE
548  if (periph->idx_buf < (trans->len_r - 3))
549  {
550  regs->CR2 |= I2C_CR2_BIT_ITBUFEN;
551  }
552  else // idx >= len-3: there are 3 bytes to be read
553  {
554  // We want to halt I2C to have sufficient time to clear ACK, so:
555  // Stop listening to RXNE as it will be triggered infinitely since we did not empty the buffer
556  // on the next (second in buffer) received byte BTF will be set (buffer full and I2C halted)
557  regs->CR2 &= ~ I2C_CR2_BIT_ITBUFEN;
558  }
559  }
560  // Buffer is full while this was not a RXNE interrupt
561  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BIT_BTF, SR1) )
562  {
563  // Now the shift register and data register contain data(n-2) and data(n-1)
564  // And I2C is halted so we have time
565 
566  // --- Make absolutely sure the next 2 I2C actions are performed with no delay
567  __disable_irq();
568 
569  // First we clear the ACK while the SCL is held low by BTF
570  regs->CR1 &= ~ I2C_CR1_BIT_ACK;
571 
572  // Now that ACK is cleared we read one byte: instantly the last byte is being clocked in...
573  trans->buf[periph->idx_buf] = regs->DR;
574  periph->idx_buf ++;
575 
576  // Now the last byte is being clocked. Stop in MUST be set BEFORE the transfer of the last byte is complete
577  PPRZ_I2C_SEND_STOP(regs);
578 
579  __enable_irq();
580  // --- end of critical zone -----------
581 
582  // read the byte2 we had in the buffer (BTF means 2 bytes available)
583  trans->buf[periph->idx_buf] = regs->DR;
584  periph->idx_buf ++;
585 
586  // Ask for an interrupt to read the last byte (which is normally still busy now)
587  // The last byte will be received with RXNE
588  regs->CR2 |= I2C_CR2_BIT_ITBUFEN;
589  }
590  else
591  {
592  // Error
593 #ifdef I2C_DEBUG_LED
594  LED2_ON();
595  LED1_ON();
596  LED2_OFF();
597  LED1_OFF();
598 #endif
599  }
600 
601  return STMI2C_SubTra_Busy;
602 }
603 
604 
605 static inline void stmi2c_clear_pending_interrupts(I2C_TypeDef *regs)
606 {
607  uint16_t SR1 = regs->SR1;
608 
609  regs->CR2 &= ~ I2C_CR2_BIT_ITBUFEN; // Disable TXE, RXNE
610 
611 
612  // Start Condition Was Generated
613  if (BIT_X_IS_SET_IN_REG( I2C_SR1_BIT_SB, SR1 ) )
614  {
615  // SB: cleared by software when reading SR1 and writing to DR
616  regs->DR = 0x00;
617  }
618  // Address Was Sent
620  {
621  // ADDR: Cleared by software when reading SR1 and then SR2
622  uint16_t SR2 __attribute__ ((unused)) = regs->SR2;
623  }
624  // Byte Transfer Finished
626  {
627  // SB: cleared by software when reading SR1 and reading/writing to DR
628  uint8_t dummy __attribute__ ((unused)) = regs->DR;
629  regs->DR = 0x00;
630  }
631 }
632 
633 
634 static inline void i2c_error(struct i2c_periph *periph);
635 
636 static inline void i2c_irq(struct i2c_periph *periph)
637 {
638 
639  /*
640  There are 7 possible reasons to get here:
641 
642  If IT_EV_FEN
643  -------------------------
644 
645  We are always interested in all IT_EV_FEV: all are required.
646 
647  1) SB // Start Condition Success in Master mode
648  2) ADDR // Address sent received Acknoledge
649  [3 ADDR10] // -- 10bit address stuff
650  [4 STOPF] // -- only for slaves: master has no stop interrupt
651  5) BTF // I2C has stopped working (it is waiting for new data, all buffers are tx_empty/rx_full)
652 
653  // Beware: using the buffered I2C has some interesting properties:
654  -in master receive mode: BTF only occurs after the 2nd received byte: after the first byte is received it is
655  in RD but the I2C can still receive a second byte. Only when the 2nd byte is received while the RxNE is 1
656  then a BTF occurs (I2C can not continue receiving bytes or they will get lost). During BTF I2C is halted (SCL held low)
657  -in master transmitmode: when writing a byte to WD, you instantly get a new TxE interrupt while the first is not
658  transmitted yet. The byte was pushed to the I2C shift register and the buffer is ready for more. You can already
659  fill new data in the buffer while the first is still being transmitted for max performance transmission.
660 
661  // Beware: besides data buffering you can/must plan several consecutive actions. You can send 2 bytes to the buffer, ask for a stop and
662  a new start in one go.
663 
664  -thanks to / because of this buffering and event sheduling there is not 1 interrupt per start / byte / stop
665  This also means you must think more in advance and a transaction could be popped from the stack even before it is
666  actually completely transmitted. But then you would not know the result yet so you have to keep it until the result
667  is known.
668 
669  // Beware: the order in which Status is read determines how flags are cleared. You should not just read SR1 & SR2 every time
670 
671  If IT_EV_FEN AND IT_EV_BUF
672  --------------------------
673 
674  Buffer event are not always wanted and are tipically switched on during longer data transfers. Make sure to turn off in time.
675 
676  6) RxNE
677  7) TxE
678 
679  --------------------------------------------------------------------------------------------------
680  // This driver uses only a subset of the pprz_i2c_states for several reasons:
681  // -we have less interrupts than the I2CStatus states (for efficiency)
682  // -STM32 has such a powerfull I2C engine with plenty of status register flags that
683  only little extra status information needs to be stored.
684 
685  // Status is re-used (abused) to remember the last COMMAND THAT WAS SENT to the STM I2C hardware.
686 
687 // TODO: check which are used
688  enum I2CStatus {
689  I2CIdle, // No more last command
690 
691  I2CStartRequested, // Last command was start
692  I2CRestartRequested, // Last command was restart
693  I2CStopRequested, // Very important to not send double stop conditions
694 
695  I2CSendingByte, // Some address/data operation
696 
697  // Following are not used
698  I2CReadingByte,
699  I2CAddrWrSent,
700  I2CAddrRdSent,
701  I2CSendingLastByte,
702  I2CReadingLastByte,
703  I2CComplete,
704  I2CFailed
705  };
706 
707  ---------
708 
709  The STM waits indefinately (holding SCL low) for user interaction:
710  a) after a master-start (waiting for address)
711  b) after an address (waiting for data)
712  not during data sending when using buffered
713  c) after the last byte is transmitted (waiting for either stop or restart)
714  not during data receiving when using buffered
715  not after the last byte is received
716 
717  -The STM I2C stalls indefinately when a stop condition was attempted that
718  did not succeed. The BUSY flag remains on.
719  -There is no STOP interrupt: use needs another way to finish.
720 
721  */
722 
723 
725  // Reading the status:
726  // - Caution: this clears several flags and can start transmissions etc...
727  // - Certain flags like STOP / (N)ACK need to be guaranteed to be set before
728  // the transmission of the byte is finished. At higher clock rates that can be
729  // quite fast: so we allow no other interrupt to be triggered in between
730  // reading the status and setting all needed flags
731 
732  // Direct Access to the I2C Registers
733  // Do not read SR2 as it might start the reading while an (n)ack bit might be needed first
734  I2C_TypeDef *regs = (I2C_TypeDef *) periph->reg_addr;
735 
736 #ifdef I2C_DEBUG_LED
737  LED1_ON();
738  LED1_OFF();
739 #endif
740 
741 
744  //
745  // TRANSACTION HANDLER
746 
747  enum STMI2CSubTransactionStatus ret = 0;
748 
750  // Nothing Left To Do
751  if (periph->trans_extract_idx == periph->trans_insert_idx)
752  {
753 #ifdef I2C_DEBUG_LED
754  LED2_ON();
755  LED1_ON();
756  LED2_OFF();
757  LED1_OFF();
758 
759  // no transaction and also an error?
760  LED_SHOW_ACTIVE_BITS(regs);
761 #endif
762 
763  // If we still get an interrupt but there are no more things to do
764  // (which can happen if an event was sheduled just before a bus error occurs)
765  // then its easy: just stop: clear all interrupt generating bits
766 
767  // Clear Running Events
769 
770  // Count The Errors
771  i2c_error(periph);
772 
773  // Mark this as a special error
774  periph->errors->unexpected_event_cnt++;
775 
776  periph->status = I2CIdle;
777 
778  // There are no transactions anymore:
779  // furtheron we need a transaction pointer: so we are not allowed to continue
780  return;
781  }
782 
783  struct i2c_transaction* trans = periph->trans[periph->trans_extract_idx];
784 
786  // If there was an error:
787  if (( regs->SR1 & I2C_SR1_BITS_ERR ) != 0x0000)
788  {
789 
790 #ifdef I2C_DEBUG_LED
791  LED1_ON();
792  LED2_ON();
793  LED1_OFF();
794  LED2_OFF();
795 
796  LED_SHOW_ACTIVE_BITS(regs);
797 #endif
798 
799  // Set result in transaction
800  trans->status = I2CTransFailed;
801 
802  // Prepare for next
803  ret = STMI2C_SubTra_Ready;
804 
805  // Make sure a TxRx does not Restart
806  trans->type = I2CTransRx;
807 
808  // Clear Running Events
810 
811  // Count The Errors
812  i2c_error(periph);
813  }
814 
815 
817  // Normal Event:
818  else
819  {
820 
821  if (trans->type == I2CTransRx) // TxRx are converted to Rx after the Tx Part
822  {
823  switch (trans->len_r)
824  {
825  case 1:
826  ret = stmi2c_read1(regs,trans);
827  break;
828  case 2:
829  ret = stmi2c_read2(regs,trans);
830  break;
831  default:
832  ret = stmi2c_readmany(regs,periph, trans);
833  break;
834  }
835  }
836  else // TxRx or Tx
837  {
838  ret = stmi2c_send(regs,periph,trans);
839  }
840  }
841 
843  // Sub-transaction has finished
844  if (ret != STMI2C_SubTra_Busy)
845  {
846  // If a restart is not needed
847  if (trans->type != I2CTransTxRx)
848  {
849  // Ready, no stop condition set yet
850  if (ret == STMI2C_SubTra_Ready)
851  {
852 
853  // Program a stop
854  PPRZ_I2C_SEND_STOP(regs);
855 
856  // Silent any BTF that would occur before STOP is executed
857  regs->DR = 0x00;
858  }
859 
860  // Jump to the next transaction
861  periph->trans_extract_idx++;
863  periph->trans_extract_idx = 0;
864 
865  // Tell everyone we are ready
866  periph->status = I2CIdle;
867 
868 
869  // if we have no more transaction to process, stop here
870  if (periph->trans_extract_idx == periph->trans_insert_idx)
871  {
872 
873 #ifdef I2C_DEBUG_LED
874  LED2_ON();
875  LED1_ON();
876  LED1_OFF();
877  LED1_ON();
878  LED1_OFF();
879  LED2_OFF();
880 #endif
881  }
882  // if not, start next transaction
883  else
884  {
885  // Restart transaction doing the Rx part now
886 // --- moved to idle function
887  PPRZ_I2C_SEND_START(periph);
888 // ------
889  }
890 
891  }
892  // RxTx -> Restart and do Rx part
893  else
894  {
895  trans->type = I2CTransRx;
896  periph->status = I2CStartRequested;
897  regs->CR1 |= I2C_CR1_BIT_START;
898 
899  // Silent any BTF that would occur before SB
900  regs->DR = 0x00;
901  }
902  }
903 
904  return;
905 }
906 
907 static inline void i2c_error(struct i2c_periph *periph)
908 {
909  uint8_t err_nr = 0;
910  periph->errors->er_irq_cnt;
911  if (I2C_GetITStatus(periph->reg_addr, I2C_IT_AF)) { /* Acknowledge failure */
912  periph->errors->ack_fail_cnt++;
913  I2C_ClearITPendingBit(periph->reg_addr, I2C_IT_AF);
914  err_nr = 1;
915  }
916  if (I2C_GetITStatus(periph->reg_addr, I2C_IT_BERR)) { /* Misplaced Start or Stop condition */
917  periph->errors->miss_start_stop_cnt++;
918  I2C_ClearITPendingBit(periph->reg_addr, I2C_IT_BERR);
919  err_nr = 2;
920  }
921  if (I2C_GetITStatus(periph->reg_addr, I2C_IT_ARLO)) { /* Arbitration lost */
922  periph->errors->arb_lost_cnt++;
923  I2C_ClearITPendingBit(periph->reg_addr, I2C_IT_ARLO);
924  err_nr = 3;
925  }
926  if (I2C_GetITStatus(periph->reg_addr, I2C_IT_OVR)) { /* Overrun/Underrun */
927  periph->errors->over_under_cnt++;
928  I2C_ClearITPendingBit(periph->reg_addr, I2C_IT_OVR);
929  err_nr = 4;
930  }
931  if (I2C_GetITStatus(periph->reg_addr, I2C_IT_PECERR)) { /* PEC Error in reception */
932  periph->errors->pec_recep_cnt++;
933  I2C_ClearITPendingBit(periph->reg_addr, I2C_IT_PECERR);
934  err_nr = 5;
935  }
936  if (I2C_GetITStatus(periph->reg_addr, I2C_IT_TIMEOUT)) { /* Timeout or Tlow error */
937  periph->errors->timeout_tlow_cnt++;
938  I2C_ClearITPendingBit(periph->reg_addr, I2C_IT_TIMEOUT);
939  err_nr = 6;
940  }
941  if (I2C_GetITStatus(periph->reg_addr, I2C_IT_SMBALERT)) { /* SMBus alert */
942  periph->errors->smbus_alert_cnt++;
943  I2C_ClearITPendingBit(periph->reg_addr, I2C_IT_SMBALERT);
944  err_nr = 7;
945  }
946 
947 #ifdef I2C_DEBUG_LED
948  LED_ERROR(20, err_nr);
949 #endif
950 
951  return;
952 
953 }
954 
955 
956 /*
957  // Make sure the bus is free before resetting (p722)
958  if (regs->SR2 & (I2C_FLAG_BUSY >> 16)) {
959  // Reset the I2C block
960  I2C_SoftwareResetCmd(periph->reg_addr, ENABLE);
961  I2C_SoftwareResetCmd(periph->reg_addr, DISABLE);
962  }
963 */
964 
965 //#endif /* USE_I2C2 */
966 
967 
968 
969 
970 #ifdef USE_I2C1
971 
972 struct i2c_errors i2c1_errors;
973 
974 void i2c1_hw_init(void) {
975 
976  i2c1.reg_addr = I2C1;
977  i2c1.init_struct = &I2C1_InitStruct;
978  i2c1.scl_pin = GPIO_Pin_6;
979  i2c1.sda_pin = GPIO_Pin_7;
980  i2c1.errors = &i2c1_errors;
981 
982  /* zeros error counter */
983  ZEROS_ERR_COUNTER(i2c1_errors);
984 
985  // Extra
986 #ifdef I2C_DEBUG_LED
987  LED_INIT();
988 #else
989 
990  /* reset peripheral to default state ( sometimes not achieved on reset :( ) */
991  //I2C_DeInit(I2C1);
992 
993  NVIC_PriorityGroupConfig(NVIC_PriorityGroup_0);
994  NVIC_InitTypeDef NVIC_InitStructure;
995 
996  /* Configure and enable I2C1 event interrupt --------------------------------*/
997  NVIC_InitStructure.NVIC_IRQChannel = I2C1_EV_IRQn;
998  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
999  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
1000  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
1001  NVIC_Init(&NVIC_InitStructure);
1002 
1003  /* Configure and enable I2C1 err interrupt ----------------------------------*/
1004  NVIC_InitStructure.NVIC_IRQChannel = I2C1_ER_IRQn;
1005  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
1006  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
1007  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
1008  NVIC_Init(&NVIC_InitStructure);
1009 
1010  /* Enable peripheral clocks -------------------------------------------------*/
1011  /* Enable I2C1 clock */
1012  RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2C1, ENABLE);
1013  /* Enable GPIOB clock */
1014  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
1015 
1016  GPIO_InitTypeDef GPIO_InitStructure;
1017  GPIO_InitStructure.GPIO_Pin = i2c1.scl_pin | i2c1.sda_pin;
1018  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
1019  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
1020  GPIO_Init(GPIOB, &GPIO_InitStructure);
1021 
1022  I2C_DeInit(I2C1);
1023 
1024  // enable peripheral
1025  I2C_Cmd(I2C1, ENABLE);
1026 
1027  I2C_Init(I2C1, i2c1.init_struct);
1028 
1029  // enable error interrupts
1030  I2C_ITConfig(I2C1, I2C_IT_ERR, ENABLE);
1031 
1032 #endif
1033 }
1034 
1035 void i2c1_ev_irq_handler(void) {
1036  i2c_irq(&i2c1);
1037 }
1038 
1039 void i2c1_er_irq_handler(void) {
1040  i2c_irq(&i2c1);
1041 }
1042 
1043 #endif /* USE_I2C1 */
1044 
1045 #ifdef USE_I2C2
1046 
1047 struct i2c_errors i2c2_errors;
1048 
1049 void i2c2_hw_init(void) {
1050 
1051  i2c2.reg_addr = I2C2;
1052  i2c2.init_struct = &I2C2_InitStruct;
1053  i2c2.scl_pin = GPIO_Pin_10;
1054  i2c2.sda_pin = GPIO_Pin_11;
1055  i2c2.errors = &i2c2_errors;
1056 
1057  /* zeros error counter */
1058  ZEROS_ERR_COUNTER(i2c2_errors);
1059 
1060  /* reset peripheral to default state ( sometimes not achieved on reset :( ) */
1061  //I2C_DeInit(I2C2);
1062 
1063  NVIC_PriorityGroupConfig(NVIC_PriorityGroup_0);
1064  NVIC_InitTypeDef NVIC_InitStructure;
1065 
1066  /* Configure and enable I2C2 event interrupt --------------------------------*/
1067  NVIC_InitStructure.NVIC_IRQChannel = I2C2_EV_IRQn;
1068  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
1069  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
1070  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
1071  NVIC_Init(&NVIC_InitStructure);
1072 
1073  /* Configure and enable I2C2 err interrupt ----------------------------------*/
1074  NVIC_InitStructure.NVIC_IRQChannel = I2C2_ER_IRQn;
1075  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
1076  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
1077  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
1078  NVIC_Init(&NVIC_InitStructure);
1079 
1080  /* Enable peripheral clocks -------------------------------------------------*/
1081  /* Enable I2C2 clock */
1082  RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2C2, ENABLE);
1083  /* Enable GPIOB clock */
1084  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
1085 
1086  GPIO_InitTypeDef GPIO_InitStructure;
1087  GPIO_InitStructure.GPIO_Pin = i2c2.scl_pin | i2c2.sda_pin;
1088  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
1089  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
1090  GPIO_Init(GPIOB, &GPIO_InitStructure);
1091 
1092  I2C_DeInit(I2C2);
1093 
1094  // enable peripheral
1095  I2C_Cmd(I2C2, ENABLE);
1096 
1097  I2C_Init(I2C2, i2c2.init_struct);
1098 
1099  // enable error interrupts
1100  I2C_ITConfig(I2C2, I2C_IT_ERR, ENABLE);
1101 
1102 }
1103 
1104 
1105 
1106 void i2c2_ev_irq_handler(void) {
1107  i2c_irq(&i2c2);
1108 }
1109 
1110 void i2c2_er_irq_handler(void) {
1111  i2c_irq(&i2c2);
1112 }
1113 
1114 #endif /* USE_I2C2 */
1115 
1116 
1117 void i2c_setbitrate(struct i2c_periph *periph, int bitrate)
1118 {
1119  if (i2c_idle(periph))
1120  {
1121  if (periph == &i2c2)
1122  {
1123  I2C2_InitStruct.I2C_ClockSpeed = bitrate;
1124  I2C_Init(I2C2, i2c2.init_struct);
1125  }
1126 
1127 #ifdef I2C_DEBUG_LED
1128  __disable_irq();
1129 
1130  LED2_ON();
1131  LED1_ON();
1132  LED2_OFF();
1133  LED1_OFF();
1134  LED2_ON();
1135  LED1_ON();
1136  LED2_OFF();
1137  LED1_OFF();
1138 
1139  __enable_irq();
1140 #endif
1141 
1142  }
1143 }
1144 
1145 
1146 void i2c_event(void)
1147 {
1148  static uint32_t cnt = 0;
1149  I2C_TypeDef *regs;
1150  cnt++;
1151  if (cnt > 10000) cnt = 0;
1152 
1153 #ifndef I2C_DEBUG_LED
1154 #ifdef USE_I2C1
1155  if (i2c1.status == I2CIdle)
1156  {
1157  if (i2c_idle(&i2c1))
1158  {
1159  __disable_irq();
1160  // More work to do
1161  if (i2c1.trans_extract_idx != i2c1.trans_insert_idx)
1162  {
1163  // Restart transaction doing the Rx part now
1164  PPRZ_I2C_SEND_START(&i2c1);
1165  }
1166  __enable_irq();
1167  }
1168  }
1169 #endif
1170 #endif
1171 
1172 #ifdef USE_I2C2
1173 
1174 #ifdef I2C_DEBUG_LED
1175  if (cnt == 0)
1176  {
1177  __disable_irq();
1178 
1179  LED2_ON();
1180  LED1_ON();
1181  LED1_OFF();
1182  LED1_ON();
1183  LED1_OFF();
1184  LED1_ON();
1185  LED1_OFF();
1186  LED1_ON();
1187  LED1_OFF();
1188  if (i2c2.status == I2CIdle)
1189  {
1190  LED1_ON();
1191  LED1_OFF();
1192  }
1193  else if (i2c2.status == I2CStartRequested)
1194  {
1195  LED1_ON();
1196  LED1_OFF();
1197  LED1_ON();
1198  LED1_OFF();
1199 
1200  }
1201  LED2_OFF();
1202 
1203  //regs = (I2C_TypeDef *) i2c2.reg_addr;
1204  //LED_SHOW_ACTIVE_BITS(regs);
1205 
1206  __enable_irq();
1207  }
1208 #endif
1209 
1210 
1211  //if (i2c2.status == I2CIdle)
1212  {
1213  //if (i2c_idle(&i2c2))
1214  {
1215  //__disable_irq();
1216  // More work to do
1217  //if (i2c2.trans_extract_idx != i2c2.trans_insert_idx)
1218  {
1219  // Restart transaction doing the Rx part now
1220  //PPRZ_I2C_SEND_START(&i2c2);
1221  }
1222  //__enable_irq();
1223  }
1224  }
1225 #endif
1226 }
1227 
1229 // Implement Interface Functions
1230 
1231 bool_t i2c_submit(struct i2c_periph* periph, struct i2c_transaction* t) {
1232 
1233  uint8_t temp;
1234  temp = periph->trans_insert_idx + 1;
1235  if (temp >= I2C_TRANSACTION_QUEUE_LEN) temp = 0;
1236  if (temp == periph->trans_extract_idx)
1237  return FALSE; // queue full
1238 
1239  t->status = I2CTransPending;
1240 
1241  __disable_irq();
1242  /* put transacation in queue */
1243  periph->trans[periph->trans_insert_idx] = t;
1244  periph->trans_insert_idx = temp;
1245 
1246  /* if peripheral is idle, start the transaction */
1247  // if (PPRZ_I2C_IS_IDLE(p))
1248  if (periph->status == I2CIdle)
1249  {
1250  //if (i2c_idle(periph))
1251  {
1252 #ifdef I2C_DEBUG_LED
1253  if (periph == &i2c1)
1254  {
1255 
1256  }
1257  else
1258 #endif
1259  {
1260  PPRZ_I2C_SEND_START(periph);
1261  }
1262  }
1263  }
1264  /* else it will be started by the interrupt handler when the previous transactions completes */
1265  __enable_irq();
1266 
1267  return TRUE;
1268 }
1269 
1270 bool_t i2c_idle(struct i2c_periph* periph)
1271 {
1272  I2C_TypeDef *regs = (I2C_TypeDef *) periph->reg_addr;
1273 
1274 #ifdef I2C_DEBUG_LED
1275  if (periph == &i2c1)
1276  {
1277  return TRUE;
1278  }
1279 #endif
1280  if (periph->status == I2CIdle)
1281  return ! (BIT_X_IS_SET_IN_REG( I2C_SR2_BIT_BUSY, regs->SR2 ) );
1282  else
1283  return FALSE;
1284 }
1285 
1286 
static void i2c_irq(struct i2c_periph *periph)
unsigned short uint16_t
Definition: types.h:16
#define I2C_SR2_BIT_BUSY
#define I2C_DEBUG_LED
#define I2C1
Definition: LPC21xx.h:166
#define I2C_CR1_BIT_START
void * reg_addr
Definition: i2c.h:62
uint8_t trans_extract_idx
Definition: i2c.h:58
volatile uint16_t ack_fail_cnt
Definition: i2c.h:71
#define I2C_SR1_BITS_ERR
#define I2C_CR2_BIT_ITERREN
void i2c_event(void)
#define I2C_SR1_BIT_BTF
#define I2C_SR2_BIT_TRA
bool_t i2c_submit(struct i2c_periph *periph, struct i2c_transaction *t)
#define I2C_CR1_BIT_PE
volatile uint8_t idx_buf
Definition: i2c.h:61
static enum STMI2CSubTransactionStatus stmi2c_read2(I2C_TypeDef *regs, struct i2c_transaction *trans)
enum I2CStatus status
Definition: i2c.h:60
uint8_t slave_addr
Definition: i2c.h:43
#define FALSE
Definition: imu_chimu.h:141
static void PPRZ_I2C_SEND_STOP(I2C_TypeDef *regs)
volatile uint16_t smbus_alert_cnt
Definition: i2c.h:77
volatile uint16_t timeout_tlow_cnt
Definition: i2c.h:76
static enum STMI2CSubTransactionStatus stmi2c_send(I2C_TypeDef *regs, struct i2c_periph *periph, struct i2c_transaction *trans)
Definition: i2c.h:23
void i2c_setbitrate(struct i2c_periph *periph, int bitrate)
#define I2C_CR1_BIT_SWRST
volatile uint16_t miss_start_stop_cnt
Definition: i2c.h:72
#define I2C_CR2_BIT_ITEVTEN
bool_t i2c_idle(struct i2c_periph *periph)
unsigned long uint32_t
Definition: types.h:18
#define BIT_X_IS_SET_IN_REG(X, REG)
#define I2C_SR1_BIT_RXNE
volatile uint16_t unexpected_event_cnt
Definition: i2c.h:78
Definition: i2c.h:70
enum I2CTransactionStatus status
Definition: i2c.h:47
volatile uint16_t over_under_cnt
Definition: i2c.h:74
static void LED_SHOW_ACTIVE_BITS(I2C_TypeDef *regs)
static void stmi2c_clear_pending_interrupts(I2C_TypeDef *regs)
#define I2C_SR1_BIT_TXE
volatile uint16_t pec_recep_cnt
Definition: i2c.h:75
#define TRUE
Definition: imu_chimu.h:144
static enum STMI2CSubTransactionStatus stmi2c_readmany(I2C_TypeDef *regs, struct i2c_periph *periph, struct i2c_transaction *trans)
volatile uint32_t er_irq_cnt
Definition: i2c.h:80
volatile uint8_t buf[I2C_BUF_LEN]
Definition: i2c.h:46
STMI2CSubTransactionStatus
#define I2C_CR1_BIT_POS
uint8_t len_w
Definition: i2c.h:45
uint16_t len_r
Definition: i2c.h:44
static void LED_ERROR(uint8_t base, uint8_t nr)
unsigned char uint8_t
Definition: types.h:14
static enum STMI2CSubTransactionStatus stmi2c_read1(I2C_TypeDef *regs, struct i2c_transaction *trans)
static void LED1_ON(void)
volatile uint16_t arb_lost_cnt
Definition: i2c.h:73
static void PPRZ_I2C_SEND_START(struct i2c_periph *periph)
uint8_t trans_insert_idx
Definition: i2c.h:57
#define I2C_CR2_BIT_ITBUFEN
#define ZEROS_ERR_COUNTER(_i2c_err)
Definition: i2c.h:94
struct i2c_errors * errors
Definition: i2c.h:66
Definition: i2c.h:54
static void i2c_error(struct i2c_periph *periph)
enum I2CTransactionType type
Definition: i2c.h:42
Definition: i2c.h:10
#define I2C_TRANSACTION_QUEUE_LEN
Definition: i2c.h:51
#define I2C_CR1_BIT_STOP
#define I2C_SR2_BIT_MSL
static void LED_INIT(void)
Definition: i2c.h:9
#define I2C_CR1_BIT_ACK
#define I2C_SR1_BIT_SB
__attribute__((always_inline))
Definition: i2c_arch.c:35
static void LED1_OFF(void)
#define I2C_SR1_BIT_ADDR
struct i2c_transaction * trans[I2C_TRANSACTION_QUEUE_LEN]
Definition: i2c.h:56
static void LED2_OFF(void)
static void LED2_ON(void)