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i2c_arch.rewritten.c
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1 #include "mcu_periph/i2c.h"
2 
3 #include <stm32/rcc.h>
4 #include <stm32/gpio.h>
5 #include <stm32/flash.h>
6 #include <stm32/misc.h>
7 
8 //#define I2C_DEBUG_LED
9 
11 // TODO: remove this
12 
13 
14 #ifdef I2C_DEBUG_LED
15 
16 static inline void LED1_ON(void)
17 {
18  GPIO_WriteBit(GPIOB, GPIO_Pin_6 , Bit_SET );
19 }
20 
21 static inline void LED1_OFF(void)
22 {
23  GPIO_WriteBit(GPIOB, GPIO_Pin_6 , !Bit_SET );
24 }
25 
26 static inline void LED2_ON(void)
27 {
28  GPIO_WriteBit(GPIOB, GPIO_Pin_7 , Bit_SET );
29 }
30 
31 static inline void LED2_OFF(void)
32 {
33  GPIO_WriteBit(GPIOB, GPIO_Pin_7 , !Bit_SET );
34 }
35 
36 static inline void LED_INIT(void)
37 {
38  GPIO_InitTypeDef GPIO_InitStructure;
39  RCC_APB2PeriphClockCmd( RCC_APB2Periph_GPIOB, ENABLE);
40  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_6;
41  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
42  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
43  GPIO_Init(GPIOB, &GPIO_InitStructure);
44 
45  LED1_OFF();
46  LED2_OFF();
47 }
48 
49 
50 static inline void LED_ERROR(uint8_t base, uint8_t nr)
51 {
52  LED2_ON();
53  for (int i=0;i<(base+nr);i++)
54  {
55  LED1_ON();
56  LED1_OFF();
57  }
58  LED2_OFF();
59 }
60 #endif
61 
64 
65 #ifdef USE_I2C1
66 static I2C_InitTypeDef I2C1_InitStruct = {
67  .I2C_Mode = I2C_Mode_I2C,
68  .I2C_DutyCycle = I2C_DutyCycle_2,
69  .I2C_OwnAddress1 = 0x00,
70  .I2C_Ack = I2C_Ack_Enable,
71  .I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit,
72  .I2C_ClockSpeed = 40000
73 };
74 #endif
75 
76 #ifdef USE_I2C2
77 static I2C_InitTypeDef I2C2_InitStruct = {
78  .I2C_Mode = I2C_Mode_I2C,
79  .I2C_DutyCycle = I2C_DutyCycle_2,
80  .I2C_OwnAddress1 = 0x00,
81  .I2C_Ack = I2C_Ack_Enable,
82  .I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit,
83 // .I2C_ClockSpeed = 37500 // Like on LPC
84  .I2C_ClockSpeed = 300000
85 };
86 #endif
87 
90 
91 // Bypassing the libSTM I2C functions to have more control over the reading of registers
92 // e.g. SR1 and SR2 should not always be read together as it might unwantedly clear ADDR flags etc.
93 
94 // Referring to STM32 manual:
95 // -Doc ID 13902 Rev 11
96 
97 // Status Register 1
98 
99 #define I2C_SR1_BIT_SB (1<<0) // Start Condition Met
100 #define I2C_SR1_BIT_ADDR (1<<1) // Address Sent
101 #define I2C_SR1_BIT_BTF (1<<2) // SCL held low
102 #define I2C_SR1_BIT_RXNE (1<<6) // Data Read Available
103 #define I2C_SR1_BIT_TXE (1<<7) // TX buffer space available
104 
105 #define I2C_SR1_BIT_ERR_BUS (1<<8) // Misplaced Start/Stop (usually interference)
106 #define I2C_SR1_BIT_ERR_ARLO (1<<9) // Arbitration Lost (in multimaster) or SDA short-to-ground (in single master)
107 #define I2C_SR1_BIT_ERR_AF (1<<10) // Ack Failure (too fast/too soon/no sensor/wiring break/...)
108 #define I2C_SR1_BIT_ERR_OVR (1<<11) // Overrun [data loss] (in slave) or SCL short-to-ground (in single master)
109 
110 #define I2C_SR1_BITS_ERR ((1<<8)|(1<<9)|(1<<10)|(1<<11)|(1<<12)|(1<<14)|(1<<15))
111 
112 // Status Register 2
113 
114 #define I2C_SR2_BIT_TRA (1<<2) // Transmitting
115 #define I2C_SR2_BIT_BUSY (1<<1) // Busy
116 #define I2C_SR2_BIT_MSL (1<<0) // Master Selected
117 
118 // Control Register 1
119 
120 #define I2C_CR1_BIT_PE (1<<0) // Peripheral Enable
121 #define I2C_CR1_BIT_START (1<<8) // Generate a Start
122 #define I2C_CR1_BIT_STOP (1<<9) // Generate a Stop
123 #define I2C_CR1_BIT_ACK (1<<10) // ACK / NACK
124 #define I2C_CR1_BIT_POS (1<<11) // Ack will control not the next but secondnext received byte
125 #define I2C_CR1_BIT_SWRST (1<<15) // Clear Busy Condition when no stop was detected
126 
127 // Control Register 2
128 
129 #define I2C_CR2_BIT_ITERREN (1<<8) // Error Interrupt
130 #define I2C_CR2_BIT_ITEVTEN (1<<9) // Event Interrupt
131 #define I2C_CR2_BIT_ITBUFEN (1<<10) // Buffer Interrupt
132 
133 
134 // Bit Control
135 
136 #define BIT_X_IS_SET_IN_REG(X,REG) (((REG) & (X)) == (X))
137 
138 // Critical Zones
139 
140 #define __I2C_REG_CRITICAL_ZONE_START __disable_irq();
141 #define __I2C_REG_CRITICAL_ZONE_STOP __enable_irq();
142 
143 
146 
147 // TODO: remove debug
148 #ifdef I2C_DEBUG_LED
149 
150 static inline void LED_SHOW_ACTIVE_BITS(I2C_TypeDef *regs)
151 {
152  uint16_t CR1 = regs->CR1;
153  uint16_t SR1 = regs->SR1;
154  uint16_t SR2 = regs->SR2;
155  // Note: reading SR1 and then SR2 will clear ADDR bits
156 
157  LED1_ON();
158 
159  // 1 Start
160  if (BIT_X_IS_SET_IN_REG( I2C_SR1_BIT_SB, SR1 ) )
161  LED2_ON();
162  else
163  LED2_OFF();
164  LED2_OFF();
165 
166  // 2 Addr
168  LED2_ON();
169  else
170  LED2_OFF();
171  LED2_OFF();
172 
173  // 3 BTF
175  LED2_ON();
176  else
177  LED2_OFF();
178  LED2_OFF();
179 
180  // 4 ERROR
181  if (( SR1 & I2C_SR1_BITS_ERR ) != 0x0000)
182  LED2_ON();
183  else
184  LED2_OFF();
185  LED2_OFF();
186 
187  // Anything?
188  if (( SR1 + SR2) != 0x0000)
189  LED2_ON();
190  else
191  LED2_OFF();
192  LED2_OFF();
193 
194  LED1_OFF();
195 
196 
197  LED1_ON();
198 
199  // 1 Start
201  LED2_ON();
202  else
203  LED2_OFF();
204  LED2_OFF();
205 
206  // 2 Stop
208  LED2_ON();
209  else
210  LED2_OFF();
211  LED2_OFF();
212 
213  // 3 Busy
215  LED2_ON();
216  else
217  LED2_OFF();
218  LED2_OFF();
219 
220  // 4 Tra
222  LED2_ON();
223  else
224  LED2_OFF();
225  LED2_OFF();
226 
227  // 5 Master
229  LED2_ON();
230  else
231  LED2_OFF();
232  LED2_OFF();
233  LED1_OFF();
234 
235 //#define I2C_DEBUG_LED_CONTROL
236 #ifdef I2C_DEBUG_LED_CONTROL
237 
238 
239  LED1_ON();
240 
241  // 1 Anything CR?
242  if (( CR1) != 0x0000)
243  LED2_ON();
244  else
245  LED2_OFF();
246  LED2_OFF();
247 
248  // 2 PE
249  if (BIT_X_IS_SET_IN_REG( I2C_CR1_BIT_PE, CR1 ) )
250  LED2_ON();
251  else
252  LED2_OFF();
253  LED2_OFF();
254 
255  // 3 SWRESET
257  LED2_ON();
258  else
259  LED2_OFF();
260  LED2_OFF();
261 
262  LED1_OFF();
263 #endif
264 
265 }
266 #endif
267 
268 static inline void PPRZ_I2C_SEND_STOP(I2C_TypeDef *regs)
269 {
270  // Man: p722: Stop generation after the current byte transfer or after the current Start condition is sent.
271  regs->CR1 |= I2C_CR1_BIT_STOP;
272 
273 #ifdef I2C_DEBUG_LED
274  LED2_ON();
275  LED1_ON();
276  LED1_OFF();
277  LED2_OFF();
278 #endif
279 }
280 
281 // (RE)START
282 
283 static inline void PPRZ_I2C_SEND_START(struct i2c_periph *periph)
284 {
285  I2C_TypeDef *regs = (I2C_TypeDef *) periph->reg_addr;
286 
287  // Reset the buffer pointer to the first byte
288  periph->idx_buf = 0;
289 
290 #ifdef I2C_DEBUG_LED
291  LED_SHOW_ACTIVE_BITS(regs);
292 
293  LED2_ON();
294  LED1_ON();
295  LED1_OFF();
296  LED1_ON();
297  LED1_OFF();
298  LED1_ON();
299  LED1_OFF();
300  LED2_OFF();
301 
302 #endif
303 
304  // Enable Error IRQ, Event IRQ but disable Buffer IRQ
305  regs->CR2 |= I2C_CR2_BIT_ITERREN;
306  regs->CR2 |= I2C_CR2_BIT_ITEVTEN;
307  regs->CR2 &= ~ I2C_CR2_BIT_ITBUFEN;
308 
309  // Issue a new start
310  regs->CR1 = (I2C_CR1_BIT_START | I2C_CR1_BIT_PE);
311  periph->status = I2CStartRequested;
312 
313 }
314 
315 // STOP
316 
319 //
320 // SUBTRANSACTION SEQUENCES
321 // -We arrive here every time a ISR is called with no error
322 
328 };
329 
330 // Doc ID 13902 Rev 11 p 710/1072
331 // Transfer Sequence Diagram for Master Transmitter
332 static inline enum STMI2CSubTransactionStatus stmi2c_send(I2C_TypeDef *regs, struct i2c_periph *periph, struct i2c_transaction *trans)
333 {
334  uint16_t SR1 = regs->SR1;
335 
336  // Start Condition Was Just Generated
337  if (BIT_X_IS_SET_IN_REG( I2C_SR1_BIT_SB, SR1 ) )
338  {
339  // Disable buffer interrupt
340  regs->CR2 &= ~ I2C_CR2_BIT_ITBUFEN;
341  // Send Slave address and wait for ADDR interrupt
342  regs->DR = trans->slave_addr;
343  // Document the current Status
344  periph->status = I2CAddrWrSent;
345  }
346  // Address Was Sent
347  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BIT_ADDR, SR1) )
348  {
349  // Now read SR2 to clear the ADDR status Bit
350  uint16_t SR2 __attribute__ ((unused)) = regs->SR2;
351 
352  // Maybe check we are transmitting (did not loose arbitration for instance)
353  // if (! BIT_X_IS_SET_IN_REG(I2C_SR2_BIT_TRA, SR2)) { }
354  // update: this should be caught by the ARLO error: so we will not arrive here
355 
356  // Send First max 2 bytes
357  regs->DR = trans->buf[0];
358  if (trans->len_w > 1)
359  {
360  regs->DR = trans->buf[1];
361  periph->idx_buf = 2;
362  }
363  else
364  {
365  periph->idx_buf = 1;
366  }
367 
368  // Enable buffer-space available interrupt
369  // only if there is more to send: wait for TXE, no more to send: wait for BTF
370  if ( periph->idx_buf < trans->len_w)
371  regs->CR2 |= I2C_CR2_BIT_ITBUFEN;
372 
373  // Document the current Status
374  periph->status = I2CSendingByte;
375  }
376  // The buffer is not full anymore AND we were not waiting for BTF
378  {
379  // Send the next byte
380  regs->DR = trans->buf[periph->idx_buf];
381  periph->idx_buf++;
382 
383  // All bytes Sent? Then wait for BTF instead
384  if ( periph->idx_buf >= trans->len_w)
385  {
386  // Not interested anymore to know the buffer has space left
387  regs->CR2 &= ~ I2C_CR2_BIT_ITBUFEN;
388  // Next interrupt will be BTF (or error)
389  }
390  }
391  // BTF: means last byte was sent
392  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BIT_BTF, SR1) )
393  {
394  if (trans->type == I2CTransTx)
395  {
396  // Tell the driver we are ready
397  trans->status = I2CTransSuccess;
398  }
399  // Otherwise we still need to do the receiving part
400 
401  return STMI2C_SubTra_Ready;
402  }
403  else // Event Logic Error
404  {
405  return STMI2C_SubTra_Error;
406  }
407 
408  return STMI2C_SubTra_Busy;
409 }
410 
411 // Doc ID 13902 Rev 11 p 714/1072
412 // Transfer Sequence Diagram for Master Receiver for N=1
413 static inline enum STMI2CSubTransactionStatus stmi2c_read1(I2C_TypeDef *regs, struct i2c_periph *periph, struct i2c_transaction *trans)
414 {
415  uint16_t SR1 = regs->SR1;
416 
417  // Start Condition Was Just Generated
418  if (BIT_X_IS_SET_IN_REG( I2C_SR1_BIT_SB, SR1 ) )
419  {
420  regs->CR2 &= ~ I2C_CR2_BIT_ITBUFEN;
421  regs->DR = trans->slave_addr | 0x01;
422 
423  // Document the current Status
424  periph->status = I2CAddrRdSent;
425  }
426  // Address Was Sent
427  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BIT_ADDR, SR1) )
428  {
429  // First Clear the ACK bit: after the next byte we do not want new bytes
430  regs->CR1 &= ~ I2C_CR1_BIT_POS;
431  regs->CR1 &= ~ I2C_CR1_BIT_ACK;
432 
433  // --- next to steps MUST be executed together to avoid missing the stop
435 
436  // Only after setting ACK, read SR2 to clear the ADDR (next byte will start arriving)
437  uint16_t SR2 __attribute__ ((unused)) = regs->SR2;
438 
439  // Schedule a Stop
440  PPRZ_I2C_SEND_STOP(regs);
441 
443  // --- end of critical zone -----------
444 
445  // Enable the RXNE: it will trigger as soon as the 1 byte is received to get the result
446  regs->CR2 |= I2C_CR2_BIT_ITBUFEN;
447 
448  // Document the current Status
449  periph->status = I2CReadingLastByte;
450  }
451  // As soon as there is 1 byte ready to read, we have our byte
452  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BIT_RXNE, SR1) )
453  {
454  regs->CR2 &= ~ I2C_CR2_BIT_ITBUFEN;
455  trans->buf[0] = regs->DR;
456 
457  // We got all the results (stop condition might still be in progress but this is the last interrupt)
458  trans->status = I2CTransSuccess;
459 
460  // Document the current Status:
461  // -the stop was actually already requested in the previous step
462  periph->status = I2CStopRequested;
463 
465  }
466  else // Event Logic Error
467  {
468  return STMI2C_SubTra_Error;
469  }
470 
471  return STMI2C_SubTra_Busy;
472 }
473 
474 // Doc ID 13902 Rev 11 p 713/1072
475 // Transfer Sequence Diagram for Master Receiver for N=2
476 static inline enum STMI2CSubTransactionStatus stmi2c_read2(I2C_TypeDef *regs, struct i2c_periph *periph, struct i2c_transaction *trans)
477 {
478  uint16_t SR1 = regs->SR1;
479 
480  // Start Condition Was Just Generated
481  if (BIT_X_IS_SET_IN_REG( I2C_SR1_BIT_SB, SR1 ) )
482  {
483  // according to the datasheet: instantly shedule a NAK on the second received byte:
484  regs->CR2 &= ~ I2C_CR2_BIT_ITBUFEN;
485  regs->CR1 |= I2C_CR1_BIT_ACK;
486  regs->CR1 |= I2C_CR1_BIT_POS;
487  regs->DR = trans->slave_addr | 0x01;
488 
489  // Document the current Status
490  periph->status = I2CAddrRdSent;
491  }
492  // Address Was Sent
493  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BIT_ADDR, SR1) )
494  {
495  // --- make absolutely sure this command is not delayed too much after the previous:
496  // --- the NAK bits must be set before the first byte arrived: allow other interrupts here
498 
499  // if transfer of DR was finished already then we will get too many bytes
500  // BEFORE clearing ACK, read SR2 to clear the ADDR (next byte will start arriving)
501  // clearing ACK after the byte transfer has already started will NACK the next (2nd)
502  uint16_t SR2 __attribute__ ((unused)) = regs->SR2;
503 
504  // NOT First Clear the ACK bit but only AFTER clearing ADDR
505  regs->CR1 &= ~ I2C_CR1_BIT_ACK;
506 
507  // Disable the RXNE and wait for BTF
508  regs->CR2 &= ~ I2C_CR2_BIT_ITBUFEN;
509 
511  // --- end of critical zone -----------
512 
513  // We do not set the RxE but wait for both bytes to arrive using BTF
514 
515  // Document the current Status
516  periph->status = I2CReadingByte;
517  }
518  // Receive buffer if full, master is halted: BTF
519  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BIT_BTF, SR1) )
520  {
521  // Stop condition MUST be set BEFORE reading the DR
522  // otherwise since there is new buffer space a new byte will be read
523  PPRZ_I2C_SEND_STOP(regs);
524 
525  // Document the current Status
526  periph->status = I2CStopRequested;
527 
528  trans->buf[0] = regs->DR;
529  trans->buf[1] = regs->DR;
530 
531  // We got all the results
532  trans->status = I2CTransSuccess;
533 
535  }
536  else // Event Logic Error
537  {
538  return STMI2C_SubTra_Error;
539  }
540 
541  return STMI2C_SubTra_Busy;
542 }
543 
544 // Doc ID 13902 Rev 11 p 712/1072
545 // Transfer Sequence Diagram for Master Receiver for N>2
546 static inline enum STMI2CSubTransactionStatus stmi2c_readmany(I2C_TypeDef *regs, struct i2c_periph *periph, struct i2c_transaction *trans)
547 {
548  uint16_t SR1 = regs->SR1;
549 
550  // Start Condition Was Just Generated
551  if (BIT_X_IS_SET_IN_REG( I2C_SR1_BIT_SB, SR1 ) )
552  {
553  regs->CR2 &= ~ I2C_CR2_BIT_ITBUFEN;
554  // The first data byte will be acked in read many so the slave knows it should send more
555  regs->CR1 &= ~ I2C_CR1_BIT_POS;
556  regs->CR1 |= I2C_CR1_BIT_ACK;
557  // Clear the SB flag
558  regs->DR = trans->slave_addr | 0x01;
559 
560  // Document the current Status
561  periph->status = I2CAddrRdSent;
562  }
563  // Address Was Sent
564  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BIT_ADDR, SR1) )
565  {
566  periph->idx_buf = 0;
567 
568  // Enable RXNE: receive an interrupt any time a byte is available
569  // only enable if MORE than 3 bytes need to be read
570  if (periph->idx_buf < (trans->len_r - 3))
571  {
572  regs->CR2 |= I2C_CR2_BIT_ITBUFEN;
573  }
574 
575  // ACK is still on to get more DATA
576  // Read SR2 to clear the ADDR (next byte will start arriving)
577  uint16_t SR2 __attribute__ ((unused)) = regs->SR2;
578 
579  // Document the current Status
580  periph->status = I2CReadingByte;
581  }
582  // one or more bytes are available AND we were interested in Buffer interrupts
584  {
585  // read byte until 3 bytes remain to be read (e.g. len_r = 6, -> idx=3 means idx 3,4,5 = 3 remain to be read
586  if (periph->idx_buf < (trans->len_r - 3))
587  {
588  trans->buf[periph->idx_buf] = regs->DR;
589  periph->idx_buf ++;
590  }
591  // from : 3bytes -> last byte: do nothing
592  //
593  // finally: this was the last byte
594  else if (periph->idx_buf >= (trans->len_r - 1))
595  {
596  regs->CR2 &= ~ I2C_CR2_BIT_ITBUFEN;
597 
598  // Last Value
599  trans->buf[periph->idx_buf] = regs->DR;
600  periph->idx_buf ++;
601 
602  // We got all the results
603  trans->status = I2CTransSuccess;
604 
606  }
607 
608  // Check for end of transaction: start waiting for BTF instead of RXNE
609  if (periph->idx_buf < (trans->len_r - 3))
610  {
611  regs->CR2 |= I2C_CR2_BIT_ITBUFEN;
612  }
613  else // idx >= len-3: there are 3 bytes to be read
614  {
615  // We want to halt I2C to have sufficient time to clear ACK, so:
616  // Stop listening to RXNE as it will be triggered infinitely since we did not empty the buffer
617  // on the next (second in buffer) received byte BTF will be set (buffer full and I2C halted)
618  regs->CR2 &= ~ I2C_CR2_BIT_ITBUFEN;
619  }
620  }
621  // Buffer is full while this was not a RXNE interrupt
622  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BIT_BTF, SR1) )
623  {
624  // Now the shift register and data register contain data(n-2) and data(n-1)
625  // And I2C is halted so we have time
626 
627  // --- Make absolutely sure the next 2 I2C actions are performed with no delay
629 
630  // First we clear the ACK while the SCL is held low by BTF
631  regs->CR1 &= ~ I2C_CR1_BIT_ACK;
632 
633  // Now that ACK is cleared we read one byte: instantly the last byte is being clocked in...
634  trans->buf[periph->idx_buf] = regs->DR;
635  periph->idx_buf ++;
636 
637  // Now the last byte is being clocked. Stop in MUST be set BEFORE the transfer of the last byte is complete
638  PPRZ_I2C_SEND_STOP(regs);
639 
641  // --- end of critical zone -----------
642 
643  // Document the current Status
644  periph->status = I2CStopRequested;
645 
646  // read the byte2 we had in the buffer (BTF means 2 bytes available)
647  trans->buf[periph->idx_buf] = regs->DR;
648  periph->idx_buf ++;
649 
650  // Ask for an interrupt to read the last byte (which is normally still busy now)
651  // The last byte will be received with RXNE
652  regs->CR2 |= I2C_CR2_BIT_ITBUFEN;
653  }
654  else // Event Logic Error
655  {
656  return STMI2C_SubTra_Error;
657  }
658 
659  return STMI2C_SubTra_Busy;
660 }
661 
663 // Restore bus conditions to normal after errors
664 
665 static inline void i2c_error(struct i2c_periph *periph)
666 {
667  uint8_t err_nr = 0;
668  periph->errors->er_irq_cnt;
669  if (I2C_GetITStatus(periph->reg_addr, I2C_IT_AF)) { /* Acknowledge failure */
670  periph->errors->ack_fail_cnt++;
671  I2C_ClearITPendingBit(periph->reg_addr, I2C_IT_AF);
672  err_nr = 1;
673  }
674  if (I2C_GetITStatus(periph->reg_addr, I2C_IT_BERR)) { /* Misplaced Start or Stop condition */
675  periph->errors->miss_start_stop_cnt++;
676  I2C_ClearITPendingBit(periph->reg_addr, I2C_IT_BERR);
677  err_nr = 2;
678  }
679  if (I2C_GetITStatus(periph->reg_addr, I2C_IT_ARLO)) { /* Arbitration lost */
680  periph->errors->arb_lost_cnt++;
681  I2C_ClearITPendingBit(periph->reg_addr, I2C_IT_ARLO);
682  err_nr = 3;
683  }
684  if (I2C_GetITStatus(periph->reg_addr, I2C_IT_OVR)) { /* Overrun/Underrun */
685  periph->errors->over_under_cnt++;
686  I2C_ClearITPendingBit(periph->reg_addr, I2C_IT_OVR);
687  err_nr = 4;
688  }
689  if (I2C_GetITStatus(periph->reg_addr, I2C_IT_PECERR)) { /* PEC Error in reception */
690  periph->errors->pec_recep_cnt++;
691  I2C_ClearITPendingBit(periph->reg_addr, I2C_IT_PECERR);
692  err_nr = 5;
693  }
694  if (I2C_GetITStatus(periph->reg_addr, I2C_IT_TIMEOUT)) { /* Timeout or Tlow error */
695  periph->errors->timeout_tlow_cnt++;
696  I2C_ClearITPendingBit(periph->reg_addr, I2C_IT_TIMEOUT);
697  err_nr = 6;
698  }
699  if (I2C_GetITStatus(periph->reg_addr, I2C_IT_SMBALERT)) { /* SMBus alert */
700  periph->errors->smbus_alert_cnt++;
701  I2C_ClearITPendingBit(periph->reg_addr, I2C_IT_SMBALERT);
702  err_nr = 7;
703  }
704 
705 #ifdef I2C_DEBUG_LED
706  LED_ERROR(20, err_nr);
707 #endif
708 
709  return;
710 }
711 
712 
713 static inline void stmi2c_clear_pending_interrupts(I2C_TypeDef *regs)
714 {
715  uint16_t SR1 = regs->SR1;
716 
717  // Certainly do not wait for buffer interrupts:
718  // -------------------------------------------
719  regs->CR2 &= ~ I2C_CR2_BIT_ITBUFEN; // Disable TXE, RXNE
720 
721  // Error interrupts are handled separately:
722  // ---------------------------------------
723 
724  // Clear Event interrupt conditions:
725  // --------------------------------
726 
727  // Start Condition Was Generated
728  if (BIT_X_IS_SET_IN_REG( I2C_SR1_BIT_SB, SR1 ) )
729  {
730  // SB: cleared by software when reading SR1 and writing to DR
731  regs->DR = 0x00;
732  }
733  // Address Was Sent
735  {
736  // ADDR: Cleared by software when reading SR1 and then SR2
737  uint16_t SR2 __attribute__ ((unused)) = regs->SR2;
738  }
739  // Byte Transfer Finished
741  {
742  // SB: cleared by software when reading SR1 and reading/writing to DR
743  uint8_t dummy __attribute__ ((unused)) = regs->DR;
744  regs->DR = 0x00;
745  }
746 
747 }
748 
749 
751 // Restore bus conditions to normal after errors
752 
753 static inline void i2c_irq(struct i2c_periph *periph)
754 {
755 
756  /*
757  There are 7 possible event reasons to get here + all errors
758 
759  If IT_EV_FEN
760  -------------------------
761 
762  We are always interested in all IT_EV_FEV: all are required.
763 
764  1) SB // Start Condition Success in Master mode
765  2) ADDR // Address sent received Acknoledge
766  [ADDR10] // -- 10bit address stuff: not used
767  [STOPF] // -- only for slaves: master has no stop interrupt: not used
768  3) BTF // I2C has stopped working (it is waiting for new data, all buffers are tx_empty/rx_full)
769 
770  // Beware: using the buffered I2C has some interesting properties:
771  -in master receive mode: BTF only occurs after the 2nd received byte: after the first byte is received it is
772  in RD but the I2C can still receive a second byte. Only when the 2nd byte is received while the RxNE is 1
773  then a BTF occurs (I2C can not continue receiving bytes or they will get lost). During BTF I2C is halted (SCL held low)
774  -in master transmit mode: when writing a byte to WD, you instantly get a new TxE interrupt while the first is not
775  transmitted yet. The byte was pushed to the I2C shift register and the buffer is ready for more. You can already
776  fill new data in the buffer while the first is still being transmitted for max performance transmission.
777 
778  // Beware: besides data buffering you can/must plan several consecutive actions. You can send 2 bytes to the buffer, ask for a stop and
779  a new start in one go.
780 
781  -thanks to / because of this buffering and event sheduling there is not 1 interrupt per start / byte / stop
782  This also means you must think more in advance and a transaction could be popped from the transaction stack even before it's
783  stop condition is actually generated.
784 
785  // Beware: the order in which Status (and other register) is read determines how flags are cleared.
786  You should NOT simply read SR1 & SR2 every time
787 
788  If IT_EV_FEN AND IT_EV_BUF
789  --------------------------
790 
791  Buffer event are not always wanted and are typically switched on during longer data transfers. Make sure to turn off in time.
792 
793  4) RxNE
794  5) TxE
795 
796  --------------------------------------------------------------------------------------------------
797 
798  The STM waits indefinately (holding SCL low) for user interaction:
799  a) after a master-start (waiting for address)
800  b) after an address (waiting for data)
801  not during data sending when using buffered
802  c) after the last byte is transmitted (waiting for either stop or restart)
803  not during data receiving when using buffered
804  not after the last byte is received
805 
806  -The STM I2C stalls indefinately when a stop condition was attempted that
807  did not succeed. The BUSY flag remains on.
808  -There is no STOP interrupt.
809 
810  Caution Reading the status:
811  - Caution: this clears several flags and can start transmissions etc...
812  - Certain flags like STOP / (N)ACK need to be guaranteed to be set before
813  the transmission of the byte is finished. At higher clock rates that can be
814  quite fast: so we allow no other interrupt to be triggered in between
815  reading the status and setting all needed flags
816 
817  */
818 
819  // Here we go ...
820 
821  // Apparently we got an I2C interrupt: EVT BUF or ERR
822 
823 #ifdef I2C_DEBUG_LED
824  // Notify ISR is triggered
825  LED1_ON();
826  LED1_OFF();
827 #endif
828 
829  // Save Some Direct Access to the I2C Registers ...
830  I2C_TypeDef *regs = (I2C_TypeDef *) periph->reg_addr;
831 
833  // Check if we were ready ...
834  if (periph->trans_extract_idx == periph->trans_insert_idx)
835  {
836  // Nothing Left To Do
837 
838 #ifdef I2C_DEBUG_LED
839  LED2_ON();
840  LED1_ON();
841  LED2_OFF();
842  LED1_OFF();
843 
844  // no transaction and also an error?
845  LED_SHOW_ACTIVE_BITS(regs);
846 #endif
847 
848  // If we still get an interrupt but there are no more things to do
849  // (which can happen if an event was sheduled just before a bus error occurs)
850  // (or can happen if both error and event interrupts were called together [the 2nd will then get this error])
851 
852  // since there is nothing more to do: its easy: just stop: clear all interrupt generating bits
853 
854  // Count The Errors
855  i2c_error(periph);
856 
857  // Clear Running Events
859 
860  // Mark this as a special error
861  periph->errors->last_unexpected_event++;
862 
863  // Document the current Status
864  periph->status = I2CIdle;
865 
866  // There are no transactions anymore: return
867  // further-on in this routine we need a transaction pointer: so we are not allowed to continue
868  return;
869  }
870 
871  // get the I2C transaction we were working on ...
872 
873  enum STMI2CSubTransactionStatus ret = 0;
874  struct i2c_transaction* trans = periph->trans[periph->trans_extract_idx];
875 
877  // If there was an error:
878  if (( regs->SR1 & I2C_SR1_BITS_ERR ) != 0x0000)
879  {
880 
881 #ifdef I2C_DEBUG_LED
882  LED1_ON();
883  LED2_ON();
884  LED1_OFF();
885  LED2_OFF();
886 
887  LED_SHOW_ACTIVE_BITS(regs);
888 #endif
889 
890  // Notify everyone about the error ...
891 
892  // Set result in transaction
893  trans->status = I2CTransFailed;
894 
895  // Document the current Status
896  periph->status = I2CFailed;
897 
898  // Make sure a TxRx does not Restart
899  trans->type = I2CTransRx;
900 
901  // Count The Errors
902  i2c_error(periph);
903 
904  // Clear Running Events
906 
907  // Now continue as if everything was normal from now on
908  ret = STMI2C_SubTra_Ready;
909 
910  }
911 
913  // Normal Event:
914  else
915  {
916 
919  //
920  // SUB-TRANSACTION HANDLER
921 
922  if (trans->type == I2CTransRx) // TxRx are converted to Rx after the Tx Part
923  {
924  switch (trans->len_r)
925  {
926  case 1:
927  ret = stmi2c_read1(regs,periph,trans);
928  break;
929  case 2:
930  ret = stmi2c_read2(regs,periph,trans);
931  break;
932  default:
933  ret = stmi2c_readmany(regs,periph,trans);
934  break;
935  }
936  }
937  else // TxRx or Tx
938  {
939  ret = stmi2c_send(regs,periph,trans);
940  }
941  }
942 
944  // Sub-transaction has finished
945  if (ret != STMI2C_SubTra_Busy)
946  {
947  // Ready or SubTraError
948  // -ready: with or without stop already asked
949 
950  // In case of unexpected event condition during subtransaction handling:
951  if (ret == STMI2C_SubTra_Error)
952  {
953  // Tell everyone about the subtransaction error:
954  // this is the previously called SPURRIOUS INTERRUPT
955  periph->status = I2CFailed;
956  trans->type = I2CTransRx; // Avoid possible restart
957  trans->status = I2CTransFailed; // Notify Ready
958  periph->errors->unexpected_event_cnt++;
959 
960  // Error
961 #ifdef I2C_DEBUG_LED
962  LED2_ON();
963  LED1_ON();
964  LED2_OFF();
965  LED1_OFF();
966 
967  LED_SHOW_ACTIVE_BITS(regs);
968 #endif
969 
970  // Clear Running Events
972  }
973 
974  // RxTx -> Restart and do Rx part
975  if (trans->type == I2CTransTxRx)
976  {
977  trans->type = I2CTransRx;
978  periph->status = I2CStartRequested;
979  regs->CR1 |= I2C_CR1_BIT_START;
980 
981  // Silent any BTF that would occur before SB
982  regs->DR = 0x00;
983  }
984  // If a restart is not needed: Rx part or Tx-only
985  else
986  {
987  // Ready, no stop condition set yet
988  if (ret == STMI2C_SubTra_Ready)
989  {
990 
991  // Program a stop
992  PPRZ_I2C_SEND_STOP(regs);
993 
994  // Silent any BTF that would occur before STOP is executed
995  regs->DR = 0x00;
996  }
997 
998  // Jump to the next transaction
999  periph->trans_extract_idx++;
1001  periph->trans_extract_idx = 0;
1002 
1003  // Tell everyone we are ready
1004  periph->status = I2CIdle;
1005 
1006 
1007  // if we have no more transaction to process, stop here
1008  if (periph->trans_extract_idx == periph->trans_insert_idx)
1009  {
1010 
1011 #ifdef I2C_DEBUG_LED
1012  LED2_ON();
1013  LED1_ON();
1014  LED1_OFF();
1015  LED1_ON();
1016  LED1_OFF();
1017  LED2_OFF();
1018 #endif
1019  }
1020  // if not, start next transaction
1021  else
1022  {
1023  // Restart transaction doing the Rx part now
1024 // --- moved to idle function
1025  PPRZ_I2C_SEND_START(periph);
1026 // ------
1027  }
1028  }
1029  }
1030 
1031  return;
1032 }
1033 
1034 
1035 /*
1036  // Make sure the bus is free before resetting (p722)
1037  if (regs->SR2 & (I2C_FLAG_BUSY >> 16)) {
1038  // Reset the I2C block
1039  I2C_SoftwareResetCmd(periph->reg_addr, ENABLE);
1040  I2C_SoftwareResetCmd(periph->reg_addr, DISABLE);
1041  }
1042 */
1043 
1044 
1045 #ifdef USE_I2C1
1046 
1047 struct i2c_errors i2c1_errors;
1048 volatile uint32_t i2c1_watchdog_counter;
1049 
1050 void i2c1_hw_init(void) {
1051 
1052  i2c1.reg_addr = I2C1;
1053  i2c1.init_struct = &I2C1_InitStruct;
1054  i2c1.scl_pin = GPIO_Pin_6;
1055  i2c1.sda_pin = GPIO_Pin_7;
1056  i2c1.errors = &i2c1_errors;
1057  i2c1_watchdog_counter = 0;
1058 
1059  /* zeros error counter */
1060  ZEROS_ERR_COUNTER(i2c1_errors);
1061 
1062  // Extra
1063 #ifdef I2C_DEBUG_LED
1064  LED_INIT();
1065 #else
1066 
1067  /* reset peripheral to default state ( sometimes not achieved on reset :( ) */
1068  //I2C_DeInit(I2C1);
1069 
1070  NVIC_PriorityGroupConfig(NVIC_PriorityGroup_0);
1071  NVIC_InitTypeDef NVIC_InitStructure;
1072 
1073  /* Configure and enable I2C1 event interrupt --------------------------------*/
1074  NVIC_InitStructure.NVIC_IRQChannel = I2C1_EV_IRQn;
1075  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
1076  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
1077  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
1078  NVIC_Init(&NVIC_InitStructure);
1079 
1080  /* Configure and enable I2C1 err interrupt ----------------------------------*/
1081  NVIC_InitStructure.NVIC_IRQChannel = I2C1_ER_IRQn;
1082  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
1083  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
1084  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
1085  NVIC_Init(&NVIC_InitStructure);
1086 
1087  /* Enable peripheral clocks -------------------------------------------------*/
1088  /* Enable I2C1 clock */
1089  RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2C1, ENABLE);
1090  /* Enable GPIOB clock */
1091  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
1092 
1093  GPIO_InitTypeDef GPIO_InitStructure;
1094  GPIO_InitStructure.GPIO_Pin = i2c1.scl_pin | i2c1.sda_pin;
1095  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
1096  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
1097  GPIO_Init(GPIOB, &GPIO_InitStructure);
1098 
1099  I2C_DeInit(I2C1);
1100 
1101  // enable peripheral
1102  I2C_Cmd(I2C1, ENABLE);
1103 
1104  I2C_Init(I2C1, i2c1.init_struct);
1105 
1106  // enable error interrupts
1107  I2C_ITConfig(I2C1, I2C_IT_ERR, ENABLE);
1108 
1109  i2c_setbitrate(&i2c2, I2C2_InitStruct.I2C_ClockSpeed);
1110 #endif
1111 }
1112 
1113 void i2c1_ev_irq_handler(void) {
1114  I2C_TypeDef *regs = (I2C_TypeDef *) i2c1.reg_addr;
1115  regs->CR2 &= ~ I2C_CR2_BIT_ITERREN;
1116  i2c_irq(&i2c1);
1117  i2c1_watchdog_counter = 0;
1118  regs->CR2 |= I2C_CR2_BIT_ITERREN;
1119 }
1120 
1121 void i2c1_er_irq_handler(void) {
1122  I2C_TypeDef *regs = (I2C_TypeDef *) i2c1.reg_addr;
1123  regs->CR2 &= ~ I2C_CR2_BIT_ITEVTEN;
1124  i2c_irq(&i2c1);
1125  i2c1_watchdog_counter = 0;
1126  regs->CR2 |= I2C_CR2_BIT_ITEVTEN;
1127 }
1128 
1129 #endif /* USE_I2C1 */
1130 
1131 #ifdef USE_I2C2
1132 
1133 struct i2c_errors i2c2_errors;
1134 volatile uint32_t i2c2_watchdog_counter;
1135 
1136 void i2c2_hw_init(void) {
1137 
1138  i2c2.reg_addr = I2C2;
1139  i2c2.init_struct = &I2C2_InitStruct;
1140  i2c2.scl_pin = GPIO_Pin_10;
1141  i2c2.sda_pin = GPIO_Pin_11;
1142  i2c2.errors = &i2c2_errors;
1143  i2c2_watchdog_counter = 0;
1144 
1145  /* zeros error counter */
1146  ZEROS_ERR_COUNTER(i2c2_errors);
1147 
1148  /* reset peripheral to default state ( sometimes not achieved on reset :( ) */
1149  //I2C_DeInit(I2C2);
1150 
1151  NVIC_PriorityGroupConfig(NVIC_PriorityGroup_0);
1152  NVIC_InitTypeDef NVIC_InitStructure;
1153 
1154  /* Configure and enable I2C2 event interrupt --------------------------------*/
1155  NVIC_InitStructure.NVIC_IRQChannel = I2C2_EV_IRQn;
1156  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
1157  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
1158  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
1159  NVIC_Init(&NVIC_InitStructure);
1160 
1161  /* Configure and enable I2C2 err interrupt ----------------------------------*/
1162  NVIC_InitStructure.NVIC_IRQChannel = I2C2_ER_IRQn;
1163  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
1164  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
1165  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
1166  NVIC_Init(&NVIC_InitStructure);
1167 
1168  /* Enable peripheral clocks -------------------------------------------------*/
1169  /* Enable I2C2 clock */
1170  RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2C2, ENABLE);
1171  /* Enable GPIOB clock */
1172  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
1173 
1174  GPIO_InitTypeDef GPIO_InitStructure;
1175  GPIO_InitStructure.GPIO_Pin = i2c2.scl_pin | i2c2.sda_pin;
1176  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
1177  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
1178  GPIO_Init(GPIOB, &GPIO_InitStructure);
1179 
1180  I2C_DeInit(I2C2);
1181 
1182  // enable peripheral
1183  I2C_Cmd(I2C2, ENABLE);
1184 
1185  I2C_Init(I2C2, i2c2.init_struct);
1186 
1187  // enable error interrupts
1188  I2C_ITConfig(I2C2, I2C_IT_ERR, ENABLE);
1189 
1190  i2c_setbitrate(&i2c2, I2C2_InitStruct.I2C_ClockSpeed);
1191 }
1192 
1193 void i2c2_ev_irq_handler(void) {
1194  I2C_TypeDef *regs = (I2C_TypeDef *) i2c2.reg_addr;
1195  regs->CR2 &= ~ I2C_CR2_BIT_ITERREN;
1196  i2c_irq(&i2c2);
1197  i2c2_watchdog_counter = 0;
1198  regs->CR2 |= I2C_CR2_BIT_ITERREN;
1199 }
1200 
1201 void i2c2_er_irq_handler(void) {
1202  I2C_TypeDef *regs = (I2C_TypeDef *) i2c2.reg_addr;
1203  regs->CR2 &= ~ I2C_CR2_BIT_ITEVTEN;
1204  i2c_irq(&i2c2);
1205  i2c2_watchdog_counter = 0;
1206  regs->CR2 |= I2C_CR2_BIT_ITEVTEN;
1207 }
1208 
1209 #endif /* USE_I2C2 */
1210 
1212 // Set Bitrate to Match your application:
1213 // -short wires, low capacitance bus: IMU: high speed
1214 // -long wires with a lot of capacitance: motor controller: put speed as low as possible
1215 
1216 void i2c_setbitrate(struct i2c_periph *periph, int bitrate)
1217 {
1218  // If NOT Busy
1219  if (i2c_idle(periph))
1220  {
1221  volatile int devider;
1222  volatile int risetime;
1223 
1224  I2C_TypeDef *regs = (I2C_TypeDef *) periph->reg_addr;
1225 
1226  // store (just for fun)
1227  I2C2_InitStruct.I2C_ClockSpeed = bitrate;
1228 
1229 /*****************************************************
1230  Bitrate:
1231 
1232  -CR2 + CCR + TRISE registers
1233  -only change when PE=0
1234 
1235  e.g.
1236 
1237  10kHz: 36MHz + Standard 0x708 + 0x25
1238  70kHz: 36MHz + Standard 0x101 +
1239  400kHz: 36MHz + Fast 0x1E + 0xb
1240 
1241  // 1) Program peripheral input clock CR2: to get correct timings
1242  // 2) Configure clock control registers
1243  // 3) Configure rise time register
1244 ******************************************************/
1245 
1246  if (bitrate < 3000)
1247  bitrate = 3000;
1248 
1249  // 36MHz, fast scl: 2counts low 1 count high -> / 3:
1250  devider = 18000 / (bitrate/1000);
1251 
1252  // never allow faster than 600kbps
1253  if (devider < 20)
1254  devider = 20;
1255 
1256  // no overflow either
1257  if (devider >=4095)
1258  devider = 4095;
1259 
1260  // risetime can be up to 1/6th of the period
1261  risetime = 1000000 / (bitrate/1000) / 6 / 28;
1262 
1263  if (risetime < 10)
1264  risetime = 10;
1265 
1266  // more will overflow the register: for more you should lower the FREQ
1267  if (risetime >=31)
1268  risetime = 31;
1269 
1270  // we do not expect an interrupt as the interface should have been idle, but just in case...
1271  __disable_irq(); // this code is in user space:
1272 
1273  // CCR can only be written when PE is disabled
1274  // p731 note 5
1275  regs->CR1 &= ~ I2C_CR1_BIT_PE;
1276 
1277  // 1)
1278  regs->CR2 = 0x0324;
1279  // 2)
1280  //regs->CCR = 0x8000 + devider;
1281  regs->CCR = 0x0000 + devider;
1282  // 3)
1283  regs->TRISE = risetime;
1284 
1285  // Re-Enable
1286  regs->CR1 |= I2C_CR1_BIT_PE;
1287 
1288  __enable_irq();
1289 
1290 #ifdef I2C_DEBUG_LED
1291  __disable_irq(); // this code is in user space:
1292 
1293  LED2_ON();
1294  LED1_ON();
1295  LED2_OFF();
1296  LED1_OFF();
1297  LED2_ON();
1298  LED1_ON();
1299  LED2_OFF();
1300  LED1_OFF();
1301 
1302  __enable_irq();
1303 #endif
1304 
1305  }
1306 }
1307 
1308 
1309 // TODO: TODO: TODO:
1310 // Watchdog timer
1311 void i2c_event(void)
1312 {
1313 #ifdef USE_I2C1
1314  i2c1_watchdog_counter++;
1315 #endif
1316 
1317 #ifdef USE_I2C2
1318  i2c2_watchdog_counter++;
1319 
1320  if (i2c2_watchdog_counter > 10000)
1321  {
1322  i2c2.errors->timeout_tlow_cnt++;
1323  i2c2_watchdog_counter = 0;
1324  }
1325 
1326 
1327 #ifdef I2C_DEBUG_LED
1328  if (i2c2_watchdog_counter == 0)
1329  {
1330  __disable_irq();
1331 
1332  LED2_ON();
1333  LED1_ON();
1334  LED1_OFF();
1335  LED1_ON();
1336  LED1_OFF();
1337  LED1_ON();
1338  LED1_OFF();
1339  LED1_ON();
1340  LED1_OFF();
1341  if (i2c2.status == I2CIdle)
1342  {
1343  LED1_ON();
1344  LED1_OFF();
1345  }
1346  else if (i2c2.status == I2CStartRequested)
1347  {
1348  LED1_ON();
1349  LED1_OFF();
1350  LED1_ON();
1351  LED1_OFF();
1352 
1353  }
1354  LED2_OFF();
1355 
1356  //regs = (I2C_TypeDef *) i2c2.reg_addr;
1357  //LED_SHOW_ACTIVE_BITS(regs);
1358 
1359  __enable_irq();
1360  }
1361 #endif
1362 
1363 
1364  //if (i2c2.status == I2CIdle)
1365  {
1366  //if (i2c_idle(&i2c2))
1367  {
1368  //__disable_irq();
1369  // More work to do
1370  //if (i2c2.trans_extract_idx != i2c2.trans_insert_idx)
1371  {
1372  // Restart transaction doing the Rx part now
1373  //PPRZ_I2C_SEND_START(&i2c2);
1374  }
1375  //__enable_irq();
1376  }
1377  }
1378 #endif
1379 }
1380 
1382 // Implement Interface Functions
1383 
1384 bool_t i2c_submit(struct i2c_periph* periph, struct i2c_transaction* t) {
1385 
1386  uint8_t temp;
1387  temp = periph->trans_insert_idx + 1;
1388  if (temp >= I2C_TRANSACTION_QUEUE_LEN) temp = 0;
1389  if (temp == periph->trans_extract_idx)
1390  return FALSE; // queue full
1391 
1392  t->status = I2CTransPending;
1393 
1394  __disable_irq();
1395  /* put transacation in queue */
1396  periph->trans[periph->trans_insert_idx] = t;
1397  periph->trans_insert_idx = temp;
1398 
1399  /* if peripheral is idle, start the transaction */
1400  // if (PPRZ_I2C_IS_IDLE(p))
1401  if (periph->status == I2CIdle)
1402  {
1403  //if (i2c_idle(periph))
1404  {
1405 #ifdef I2C_DEBUG_LED
1406 #ifdef USE_I2C1
1407  if (periph == &i2c1)
1408  {
1409 
1410  }
1411  else
1412 #endif
1413 #endif
1414  {
1415 #ifdef I2C_DEBUG_LED
1416  LED2_ON();
1417  LED2_OFF();
1418 #endif
1419  PPRZ_I2C_SEND_START(periph);
1420  }
1421  }
1422  }
1423  /* else it will be started by the interrupt handler when the previous transactions completes */
1424  __enable_irq();
1425 
1426  return TRUE;
1427 }
1428 
1429 bool_t i2c_idle(struct i2c_periph* periph)
1430 {
1431  // This is actually a difficult function:
1432  // -simply reading the status flags can clear bits and corrupt the transaction
1433 
1434  I2C_TypeDef *regs = (I2C_TypeDef *) periph->reg_addr;
1435 
1436 #ifdef I2C_DEBUG_LED
1437 #ifdef USE_I2C1
1438  if (periph == &i2c1)
1439  {
1440  return TRUE;
1441  }
1442 #endif
1443 #endif
1444 
1445  // First we check if the software thinks it is ready
1446  if (periph->status == I2CIdle)
1447  return ! (BIT_X_IS_SET_IN_REG( I2C_SR2_BIT_BUSY, regs->SR2 ) );
1448  else
1449  return FALSE;
1450 }
1451 
1452 
void i2c_event(void)
static void LED_ERROR(uint8_t nr)
Definition: i2c_attempt1.c:46
unsigned short uint16_t
Definition: types.h:16
#define I2C_CR1_BIT_PE
#define I2C_DEBUG_LED
static void PPRZ_I2C_SEND_STOP(I2C_TypeDef *regs)
#define I2C1
Definition: LPC21xx.h:166
#define __I2C_REG_CRITICAL_ZONE_START
#define BIT_X_IS_SET_IN_REG(X, REG)
void * reg_addr
Definition: i2c.h:62
uint8_t trans_extract_idx
Definition: i2c.h:58
volatile uint16_t ack_fail_cnt
Definition: i2c.h:71
#define __I2C_REG_CRITICAL_ZONE_STOP
static void LED2_ON()
Definition: i2c_attempt1.c:22
#define I2C_SR1_BIT_SB
bool_t i2c_idle(struct i2c_periph *periph)
static enum STMI2CSubTransactionStatus stmi2c_send(I2C_TypeDef *regs, struct i2c_periph *periph, struct i2c_transaction *trans)
static void LED2_OFF(void)
Definition: i2c_attempt1.c:27
static void PPRZ_I2C_SEND_START(struct i2c_periph *periph)
volatile uint8_t idx_buf
Definition: i2c.h:61
#define I2C_CR2_BIT_ITEVTEN
enum I2CStatus status
Definition: i2c.h:60
uint8_t slave_addr
Definition: i2c.h:43
static void i2c_error(struct i2c_periph *periph)
#define FALSE
Definition: imu_chimu.h:141
#define I2C_SR2_BIT_MSL
volatile uint16_t smbus_alert_cnt
Definition: i2c.h:77
volatile uint16_t timeout_tlow_cnt
Definition: i2c.h:76
Definition: i2c.h:23
#define I2C_CR1_BIT_STOP
volatile uint16_t miss_start_stop_cnt
Definition: i2c.h:72
#define I2C_CR1_BIT_POS
unsigned long uint32_t
Definition: types.h:18
volatile uint16_t unexpected_event_cnt
Definition: i2c.h:78
Definition: i2c.h:70
enum I2CTransactionStatus status
Definition: i2c.h:47
volatile uint16_t over_under_cnt
Definition: i2c.h:74
static void LED_SHOW_ACTIVE_BITS(I2C_TypeDef *regs)
volatile uint16_t pec_recep_cnt
Definition: i2c.h:75
#define TRUE
Definition: imu_chimu.h:144
#define I2C_SR1_BIT_BTF
static enum STMI2CSubTransactionStatus stmi2c_readmany(I2C_TypeDef *regs, struct i2c_periph *periph, struct i2c_transaction *trans)
volatile uint32_t er_irq_cnt
Definition: i2c.h:80
volatile uint8_t buf[I2C_BUF_LEN]
Definition: i2c.h:46
STMI2CSubTransactionStatus
static enum STMI2CSubTransactionStatus stmi2c_read1(I2C_TypeDef *regs, struct i2c_periph *periph, struct i2c_transaction *trans)
uint8_t len_w
Definition: i2c.h:45
static void LED1_ON(void)
Definition: i2c_attempt1.c:12
uint16_t len_r
Definition: i2c.h:44
unsigned char uint8_t
Definition: types.h:14
volatile uint16_t arb_lost_cnt
Definition: i2c.h:73
#define I2C_SR1_BIT_TXE
Definition: i2c.h:34
uint8_t trans_insert_idx
Definition: i2c.h:57
static void stmi2c_clear_pending_interrupts(I2C_TypeDef *regs)
#define I2C_SR2_BIT_TRA
#define LED_INIT(i)
Definition: led_hw.h:26
void i2c_setbitrate(struct i2c_periph *periph, int bitrate)
#define I2C_SR2_BIT_BUSY
#define I2C_CR1_BIT_ACK
#define ZEROS_ERR_COUNTER(_i2c_err)
Definition: i2c.h:94
struct i2c_errors * errors
Definition: i2c.h:66
Definition: i2c.h:54
enum I2CTransactionType type
Definition: i2c.h:42
Definition: i2c.h:10
#define I2C_CR2_BIT_ITBUFEN
#define I2C_SR1_BIT_ADDR
#define I2C_SR1_BIT_RXNE
static enum STMI2CSubTransactionStatus stmi2c_read2(I2C_TypeDef *regs, struct i2c_periph *periph, struct i2c_transaction *trans)
#define I2C_TRANSACTION_QUEUE_LEN
Definition: i2c.h:51
#define I2C_CR1_BIT_SWRST
static void i2c_irq(struct i2c_periph *periph)
static void LED1_OFF(void)
Definition: i2c_attempt1.c:17
bool_t i2c_submit(struct i2c_periph *periph, struct i2c_transaction *t)
Definition: i2c.h:9
#define I2C_CR2_BIT_ITERREN
__attribute__((always_inline))
Definition: i2c_arch.c:35
volatile uint32_t last_unexpected_event
Definition: i2c.h:79
#define I2C_CR1_BIT_START
#define I2C_SR1_BITS_ERR
struct i2c_transaction * trans[I2C_TRANSACTION_QUEUE_LEN]
Definition: i2c.h:56