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mcuconf.h
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1 /*
2  ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
3 
4  Licensed under the Apache License, Version 2.0 (the "License");
5  you may not use this file except in compliance with the License.
6  You may obtain a copy of the License at
7 
8  http://www.apache.org/licenses/LICENSE-2.0
9 
10  Unless required by applicable law or agreed to in writing, software
11  distributed under the License is distributed on an "AS IS" BASIS,
12  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  See the License for the specific language governing permissions and
14  limitations under the License.
15 */
16 
17 #ifndef _MCUCONF_H_
18 #define _MCUCONF_H_
19 
20 /*
21  * STM32F4xx drivers configuration.
22  * The following settings override the default settings present in
23  * the various device driver implementation headers.
24  * Note that the settings for each driver only have effect if the whole
25  * driver is enabled in halconf.h.
26  *
27  * IRQ priorities:
28  * 15...0 Lowest...Highest.
29  *
30  * DMA priorities:
31  * 0...3 Lowest...Highest.
32  */
33 
34 #define STM32F4xx_MCUCONF
35 
36 /*
37  * HAL driver system settings.
38  */
39 #define STM32_NO_INIT FALSE
40 #define STM32_HSI_ENABLED TRUE
41 #define STM32_LSI_ENABLED TRUE
42 #define STM32_HSE_ENABLED TRUE
43 #define STM32_LSE_ENABLED FALSE
44 #define STM32_CLOCK48_REQUIRED TRUE
45 #define STM32_SW STM32_SW_PLL
46 #define STM32_PLLSRC STM32_PLLSRC_HSE
47 #define STM32_PLLM_VALUE 24
48 #define STM32_PLLN_VALUE 336
49 #define STM32_PLLP_VALUE 2
50 #define STM32_PLLQ_VALUE 7
51 #define STM32_HPRE STM32_HPRE_DIV1
52 #define STM32_PPRE1 STM32_PPRE1_DIV4
53 #define STM32_PPRE2 STM32_PPRE2_DIV2
54 #define STM32_RTCSEL STM32_RTCSEL_LSI
55 #define STM32_RTCPRE_VALUE 8
56 #define STM32_MCO1SEL STM32_MCO1SEL_HSI
57 #define STM32_MCO1PRE STM32_MCO1PRE_DIV1
58 #define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
59 #define STM32_MCO2PRE STM32_MCO2PRE_DIV5
60 #define STM32_I2SSRC STM32_I2SSRC_CKIN
61 #define STM32_PLLI2SN_VALUE 192
62 #define STM32_PLLI2SR_VALUE 5
63 #define STM32_PVD_ENABLE FALSE
64 #define STM32_PLS STM32_PLS_LEV0
65 #define STM32_BKPRAM_ENABLE FALSE
66 
67 /*
68  * ADC driver system settings.
69  */
70 #define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV8
71 #define STM32_ADC_USE_ADC1 TRUE
72 #define STM32_ADC_USE_ADC2 FALSE
73 #define STM32_ADC_USE_ADC3 FALSE
74 #define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
75 #define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
76 #define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
77 #define STM32_ADC_ADC1_DMA_PRIORITY 2
78 #define STM32_ADC_ADC2_DMA_PRIORITY 2
79 #define STM32_ADC_ADC3_DMA_PRIORITY 2
80 #define STM32_ADC_IRQ_PRIORITY 6
81 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6
82 #define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6
83 #define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6
84 
85 /*
86  * CAN driver system settings.
87  */
88 #if USE_CAN1
89 #define STM32_CAN_USE_CAN1 TRUE
90 #else
91 #define STM32_CAN_USE_CAN1 FALSE
92 #endif
93 #if USE_CAN2
94 #define STM32_CAN_USE_CAN2 TRUE
95 #else
96 #define STM32_CAN_USE_CAN2 FALSE
97 #endif
98 #define STM32_CAN_CAN1_IRQ_PRIORITY 11
99 #define STM32_CAN_CAN2_IRQ_PRIORITY 11
100 
101 /*
102  * DAC driver system settings.
103  */
104 #define STM32_DAC_DUAL_MODE FALSE
105 #define STM32_DAC_USE_DAC1_CH1 FALSE
106 #define STM32_DAC_USE_DAC1_CH2 FALSE
107 #define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
108 #define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
109 #define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
110 #define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
111 #define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
112 #define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
113 
114 /*
115  * EXT driver system settings.
116  */
117 #define STM32_EXT_EXTI0_IRQ_PRIORITY 6
118 #define STM32_EXT_EXTI1_IRQ_PRIORITY 6
119 #define STM32_EXT_EXTI2_IRQ_PRIORITY 6
120 #define STM32_EXT_EXTI3_IRQ_PRIORITY 6
121 #define STM32_EXT_EXTI4_IRQ_PRIORITY 6
122 #define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6
123 #define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6
124 #define STM32_EXT_EXTI16_IRQ_PRIORITY 6
125 #define STM32_EXT_EXTI17_IRQ_PRIORITY 15
126 #define STM32_EXT_EXTI18_IRQ_PRIORITY 6
127 #define STM32_EXT_EXTI19_IRQ_PRIORITY 6
128 #define STM32_EXT_EXTI20_IRQ_PRIORITY 6
129 #define STM32_EXT_EXTI21_IRQ_PRIORITY 15
130 #define STM32_EXT_EXTI22_IRQ_PRIORITY 15
131 
132 /*
133  * GPT driver system settings.
134  */
135 #define STM32_GPT_USE_TIM1 FALSE
136 #define STM32_GPT_USE_TIM2 FALSE
137 #define STM32_GPT_USE_TIM3 FALSE
138 #define STM32_GPT_USE_TIM4 FALSE
139 #define STM32_GPT_USE_TIM5 FALSE
140 #define STM32_GPT_USE_TIM6 FALSE
141 #define STM32_GPT_USE_TIM7 FALSE
142 #define STM32_GPT_USE_TIM8 FALSE
143 #define STM32_GPT_USE_TIM9 FALSE
144 #define STM32_GPT_USE_TIM11 FALSE
145 #define STM32_GPT_USE_TIM12 FALSE
146 #define STM32_GPT_USE_TIM14 FALSE
147 #define STM32_GPT_TIM1_IRQ_PRIORITY 7
148 #define STM32_GPT_TIM2_IRQ_PRIORITY 7
149 #define STM32_GPT_TIM3_IRQ_PRIORITY 7
150 #define STM32_GPT_TIM4_IRQ_PRIORITY 7
151 #define STM32_GPT_TIM5_IRQ_PRIORITY 7
152 #define STM32_GPT_TIM6_IRQ_PRIORITY 7
153 #define STM32_GPT_TIM7_IRQ_PRIORITY 7
154 #define STM32_GPT_TIM8_IRQ_PRIORITY 7
155 #define STM32_GPT_TIM9_IRQ_PRIORITY 7
156 #define STM32_GPT_TIM11_IRQ_PRIORITY 7
157 #define STM32_GPT_TIM12_IRQ_PRIORITY 7
158 #define STM32_GPT_TIM14_IRQ_PRIORITY 7
159 
160 /*
161  * I2C driver system settings.
162  */
163 #if USE_I2C1
164 #define STM32_I2C_USE_I2C1 TRUE
165 #else
166 #define STM32_I2C_USE_I2C1 FALSE
167 #endif
168 #if USE_I2C2
169 #define STM32_I2C_USE_I2C2 TRUE
170 #else
171 #define STM32_I2C_USE_I2C2 FALSE
172 #endif
173 #if USE_I2C3
174 #define STM32_I2C_USE_I2C3 TRUE
175 #else
176 #define STM32_I2C_USE_I2C3 FALSE
177 #endif
178 #define STM32_I2C_BUSY_TIMEOUT 50
179 #define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
180 #define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
181 #define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
182 #define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
183 #define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
184 #define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
185 #define STM32_I2C_I2C1_IRQ_PRIORITY 5
186 #define STM32_I2C_I2C2_IRQ_PRIORITY 5
187 #define STM32_I2C_I2C3_IRQ_PRIORITY 5
188 #define STM32_I2C_I2C1_DMA_PRIORITY 3
189 #define STM32_I2C_I2C2_DMA_PRIORITY 3
190 #define STM32_I2C_I2C3_DMA_PRIORITY 3
191 #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
192 
193 /*
194  * ICU driver system settings.
195  */
196 #define STM32_ICU_USE_TIM1 FALSE
197 #define STM32_ICU_USE_TIM2 FALSE
198 #define STM32_ICU_USE_TIM3 FALSE
199 #define STM32_ICU_USE_TIM4 FALSE
200 #define STM32_ICU_USE_TIM5 FALSE
201 #define STM32_ICU_USE_TIM8 FALSE
202 #define STM32_ICU_USE_TIM9 TRUE
203 #define STM32_ICU_TIM1_IRQ_PRIORITY 7
204 #define STM32_ICU_TIM2_IRQ_PRIORITY 7
205 #define STM32_ICU_TIM3_IRQ_PRIORITY 7
206 #define STM32_ICU_TIM4_IRQ_PRIORITY 7
207 #define STM32_ICU_TIM5_IRQ_PRIORITY 7
208 #define STM32_ICU_TIM8_IRQ_PRIORITY 7
209 #define STM32_ICU_TIM9_IRQ_PRIORITY 7
210 
211 /*
212  * MAC driver system settings.
213  */
214 #define STM32_MAC_TRANSMIT_BUFFERS 2
215 #define STM32_MAC_RECEIVE_BUFFERS 4
216 #define STM32_MAC_BUFFERS_SIZE 1522
217 #define STM32_MAC_PHY_TIMEOUT 100
218 #define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
219 #define STM32_MAC_ETH1_IRQ_PRIORITY 13
220 #define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
221 
222 /*
223  * PWM driver system settings.
224  */
225 #define STM32_PWM_USE_ADVANCED FALSE
226 #define STM32_PWM_USE_TIM1 TRUE
227 #define STM32_PWM_USE_TIM2 FALSE
228 #define STM32_PWM_USE_TIM3 FALSE
229 #define STM32_PWM_USE_TIM4 TRUE
230 #define STM32_PWM_USE_TIM5 FALSE
231 #define STM32_PWM_USE_TIM8 FALSE
232 #define STM32_PWM_USE_TIM9 FALSE
233 #define STM32_PWM_TIM1_IRQ_PRIORITY 7
234 #define STM32_PWM_TIM2_IRQ_PRIORITY 7
235 #define STM32_PWM_TIM3_IRQ_PRIORITY 7
236 #define STM32_PWM_TIM4_IRQ_PRIORITY 7
237 #define STM32_PWM_TIM5_IRQ_PRIORITY 7
238 #define STM32_PWM_TIM8_IRQ_PRIORITY 7
239 #define STM32_PWM_TIM9_IRQ_PRIORITY 7
240 
241 /*
242  * SERIAL driver system settings.
243  */
244 #if USE_UART1
245 #define STM32_SERIAL_USE_USART1 TRUE
246 #else
247 #define STM32_SERIAL_USE_USART1 FALSE
248 #endif
249 #if USE_UART2
250 #define STM32_SERIAL_USE_USART2 TRUE
251 #else
252 #define STM32_SERIAL_USE_USART2 FALSE
253 #endif
254 #if USE_UART3
255 #define STM32_SERIAL_USE_USART3 TRUE
256 #else
257 #define STM32_SERIAL_USE_USART3 FALSE
258 #endif
259 #if USE_UART4
260 #define STM32_SERIAL_USE_UART4 TRUE
261 #else
262 #define STM32_SERIAL_USE_UART4 FALSE
263 #endif
264 #if USE_UART5
265 #define STM32_SERIAL_USE_UART5 TRUE
266 #else
267 #define STM32_SERIAL_USE_UART5 FALSE
268 #endif
269 #if USE_UART6
270 #define STM32_SERIAL_USE_USART6 TRUE
271 #else
272 #define STM32_SERIAL_USE_USART6 FALSE
273 #endif
274 #if USE_UART7
275 #define STM32_SERIAL_USE_UART7 TRUE
276 #else
277 #define STM32_SERIAL_USE_UART7 FALSE
278 #endif
279 #if USE_UART8
280 #define STM32_SERIAL_USE_UART8 TRUE
281 #else
282 #define STM32_SERIAL_USE_UART8 FALSE
283 #endif
284 #define STM32_SERIAL_USART1_PRIORITY 12
285 #define STM32_SERIAL_USART2_PRIORITY 12
286 #define STM32_SERIAL_USART3_PRIORITY 12
287 #define STM32_SERIAL_UART4_PRIORITY 12
288 #define STM32_SERIAL_UART5_PRIORITY 12
289 #define STM32_SERIAL_USART6_PRIORITY 12
290 #define STM32_SERIAL_UART7_PRIORITY 12
291 #define STM32_SERIAL_UART8_PRIORITY 12
292 
293 /*
294  * SPI driver system settings.
295  */
296 #if USE_SPI1
297 #define STM32_SPI_USE_SPI1 TRUE
298 #else
299 #define STM32_SPI_USE_SPI1 FALSE
300 #endif
301 #if USE_SPI2
302 #define STM32_SPI_USE_SPI2 TRUE
303 #else
304 #define STM32_SPI_USE_SPI2 FALSE
305 #endif
306 #if USE_SPI3
307 #define STM32_SPI_USE_SPI3 TRUE
308 #else
309 #define STM32_SPI_USE_SPI3 FALSE
310 #endif
311 #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
312 #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
313 #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
314 #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
315 #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
316 #define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
317 #define STM32_SPI_SPI1_DMA_PRIORITY 1
318 #define STM32_SPI_SPI2_DMA_PRIORITY 1
319 #define STM32_SPI_SPI3_DMA_PRIORITY 1
320 #define STM32_SPI_SPI1_IRQ_PRIORITY 10
321 #define STM32_SPI_SPI2_IRQ_PRIORITY 10
322 #define STM32_SPI_SPI3_IRQ_PRIORITY 10
323 #define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
324 
325 /*
326  * ST driver system settings.
327  */
328 #define STM32_ST_IRQ_PRIORITY 8
329 #define STM32_ST_USE_TIMER 2
330 
331 /*
332  * UART driver system settings.
333  */
334 #define STM32_UART_USE_USART1 FALSE
335 #define STM32_UART_USE_USART2 FALSE
336 #define STM32_UART_USE_USART3 FALSE
337 #define STM32_UART_USE_UART4 FALSE
338 #define STM32_UART_USE_UART5 FALSE
339 #define STM32_UART_USE_USART6 FALSE
340 #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) // Not used: conflict SPI1
341 #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
342 #define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
343 #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
344 #define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
345 #define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
346 #define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
347 #define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
348 #define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
349 #define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
350 #define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
351 #define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) // Not used: conflict SDIO
352 #define STM32_UART_USART1_IRQ_PRIORITY 12
353 #define STM32_UART_USART2_IRQ_PRIORITY 12
354 #define STM32_UART_USART3_IRQ_PRIORITY 12
355 #define STM32_UART_UART4_IRQ_PRIORITY 12
356 #define STM32_UART_UART5_IRQ_PRIORITY 12
357 #define STM32_UART_USART6_IRQ_PRIORITY 12
358 #define STM32_UART_USART1_DMA_PRIORITY 1
359 #define STM32_UART_USART2_DMA_PRIORITY 0
360 #define STM32_UART_USART3_DMA_PRIORITY 0
361 #define STM32_UART_UART4_DMA_PRIORITY 0
362 #define STM32_UART_UART5_DMA_PRIORITY 0
363 #define STM32_UART_USART6_DMA_PRIORITY 0
364 #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
365 
366 /*
367  * USB driver system settings.
368  */
369 #define STM32_USB_USE_OTG1 TRUE // FS, DFU_BOOT
370 #define STM32_USB_USE_OTG2 FALSE // HS
371 #define STM32_USB_OTG1_IRQ_PRIORITY 14
372 #define STM32_USB_OTG2_IRQ_PRIORITY 14
373 #define STM32_USB_OTG1_RX_FIFO_SIZE 512
374 #define STM32_USB_OTG2_RX_FIFO_SIZE 512
375 #define STM32_USB_OTG_THREAD_PRIO HIGHPRIO
376 #define STM32_USB_OTG_THREAD_STACK_SIZE 256
377 #define STM32_USB_OTGFIFO_FILL_BASEPRI 0
378 
379 /*
380  * SDC driver system settings.
381  */
382 #define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)
383 #define STM32_SDC_SDIO_DMA_PRIORITY 3
384 #define STM32_SDC_SDIO_IRQ_PRIORITY 9
385 #define STM32_SDC_CLOCK_ACTIVATION_DELAY 10
386 #define STM32_SDC_SDIO_UNALIGNED_SUPPORT FALSE
387 #define STM32_SDC_WRITE_TIMEOUT_MS 250
388 #define STM32_SDC_READ_TIMEOUT_MS 15
389 
390 /*
391  sdlog message buffer and queue configuration
392  */
393 #define SDLOG_QUEUE_BUCKETS 1024
394 #define SDLOG_MAX_MESSAGE_LEN 252
395 #define SDLOG_NUM_FILES 2
396 #define SDLOG_ALL_BUFFERS_SIZE (SDLOG_NUM_FILES*4096*2)
397 
398 
399 /*
400  * workaround hardware bug in REV.A revision of old STM32F4 (sold in 2012, early 2013)
401  */
402 
403 #define STM32_USE_REVISION_A_FIX 1
404 
405 #endif /* _MCUCONF_H_ */