Paparazzi UAS  v5.15_devel-112-g521f3cf
Paparazzi is a free software Unmanned Aircraft System.
 All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Modules Pages
LPC21xx.h File Reference
#include "lpcWD.h"
#include "lpcTMR.h"
#include "lpcUART.h"
#include "lpcI2C.h"
#include "lpcSPI.h"
#include "lpcRTC.h"
#include "lpcGPIO.h"
#include "lpcPIN.h"
#include "lpcADC.h"
#include "lpcSCB.h"
#include "lpcVIC.h"
#include "lpcCAN.h"
+ Include dependency graph for LPC21xx.h:
+ This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Macros

#define REG_8   volatile unsigned char
 
#define REG16   volatile unsigned short
 
#define REG32   volatile unsigned long
 
#define WD   ((wdRegs_t *)0xE0000000)
 
#define WDMOD   WD->mod /* Watchdog Mode Register */
 
#define WDTC   WD->tc /* Watchdog Time Constant Register */
 
#define WDFEED   WD->feed /* Watchdog Feed Register */
 
#define WDTV   WD->tv /* Watchdog Time Value Register */
 
#define TMR0   ((pwmTmrRegs_t *)0xE0004000)
 
#define T0IR   TMR0->ir /* Interrupt Register */
 
#define T0TCR   TMR0->tcr /* Timer Control Register */
 
#define T0TC   TMR0->tc /* Timer Counter */
 
#define T0PR   TMR0->pr /* Prescale Register */
 
#define T0PC   TMR0->pc /* Prescale Counter Register */
 
#define T0MCR   TMR0->mcr /* Match Control Register */
 
#define T0MR0   TMR0->mr0 /* Match Register 0 */
 
#define T0MR1   TMR0->mr1 /* Match Register 1 */
 
#define T0MR2   TMR0->mr2 /* Match Register 2 */
 
#define T0MR3   TMR0->mr3 /* Match Register 3 */
 
#define T0CCR   TMR0->ccr /* Capture Control Register */
 
#define T0CR0   TMR0->cr0 /* Capture Register 0 */
 
#define T0CR1   TMR0->cr1 /* Capture Register 1 */
 
#define T0CR2   TMR0->cr2 /* Capture Register 2 */
 
#define T0CR3   TMR0->cr3 /* Capture Register 3 */
 
#define T0EMR   TMR0->emr /* External Match Register */
 
#define TMR1   ((pwmTmrRegs_t *)0xE0008000)
 
#define T1IR   TMR1->ir /* Interrupt Register */
 
#define T1TCR   TMR1->tcr /* Timer Control Register */
 
#define T1TC   TMR1->tc /* Timer Counter */
 
#define T1PR   TMR1->pr /* Prescale Register */
 
#define T1PC   TMR1->pc /* Prescale Counter Register */
 
#define T1MCR   TMR1->mcr /* Match Control Register */
 
#define T1MR0   TMR1->mr0 /* Match Register 0 */
 
#define T1MR1   TMR1->mr1 /* Match Register 1 */
 
#define T1MR2   TMR1->mr2 /* Match Register 2 */
 
#define T1MR3   TMR1->mr3 /* Match Register 3 */
 
#define T1CCR   TMR1->ccr /* Capture Control Register */
 
#define T1CR0   TMR1->cr0 /* Capture Register 0 */
 
#define T1CR1   TMR1->cr1 /* Capture Register 1 */
 
#define T1CR2   TMR1->cr2 /* Capture Register 2 */
 
#define T1CR3   TMR1->cr3 /* Capture Register 3 */
 
#define T1EMR   TMR1->emr /* External Match Register */
 
#define PWM   ((pwmTmrRegs_t *)0xE0014000)
 
#define PWMIR   PWM->ir /* Interrupt Register */
 
#define PWMTCR   PWM->tcr /* Timer Control Register */
 
#define PWMTC   PWM->tc /* Timer Counter */
 
#define PWMPR   PWM->pr /* Prescale Register */
 
#define PWMPC   PWM->pc /* Prescale Counter Register */
 
#define PWMMCR   PWM->mcr /* Match Control Register */
 
#define PWMMR0   PWM->mr0 /* Match Register 0 */
 
#define PWMMR1   PWM->mr1 /* Match Register 1 */
 
#define PWMMR2   PWM->mr2 /* Match Register 2 */
 
#define PWMMR3   PWM->mr3 /* Match Register 3 */
 
#define PWMMR4   PWM->mr4 /* Match Register 4 */
 
#define PWMMR5   PWM->mr5 /* Match Register 5 */
 
#define PWMMR6   PWM->mr6 /* Match Register 6 */
 
#define PWMPCR   PWM->pcr /* Control Register */
 
#define PWMLER   PWM->ler /* Latch Enable Register */
 
#define UART0_BASE   ((uartRegs_t *)0xE000C000)
 
#define U0_PINSEL   (0x00000005) /* PINSEL0 Value for UART0 */
 
#define U0_PINMASK   (0x0000000F) /* PINSEL0 Mask for UART0 */
 
#define U0_PINSEL_RX   (0x00000004) /* PINSEL0 Value for UART0 RX only */
 
#define U0_PINMASK_RX   (0x0000000C) /* PINSEL0 Mask for UART0 RX only */
 
#define U0RBR   UART0_BASE->rbr /* Receive Buffer Register */
 
#define U0THR   UART0_BASE->thr /* Transmit Holding Register */
 
#define U0IER   UART0_BASE->ier /* Interrupt Enable Register */
 
#define U0IIR   UART0_BASE->iir /* Interrupt ID Register */
 
#define U0FCR   UART0_BASE->fcr /* FIFO Control Register */
 
#define U0LCR   UART0_BASE->lcr /* Line Control Register */
 
#define U0LSR   UART0_BASE->lsr /* Line Status Register */
 
#define U0SCR   UART0_BASE->scr /* Scratch Pad Register */
 
#define U0DLL   UART0_BASE->dll /* Divisor Latch Register (LSB) */
 
#define U0DLM   UART0_BASE->dlm /* Divisor Latch Register (MSB) */
 
#define UART1_BASE   ((uartRegs_t *)0xE0010000)
 
#define U1_PINSEL   (0x00050000) /* PINSEL0 Value for UART1 */
 
#define U1_PINMASK   (0x000F0000) /* PINSEL0 Mask for UART1 */
 
#define U1_PINSEL_RX   (0x00040000) /* PINSEL0 Value for UART1 RX only */
 
#define U1_PINMASK_RX   (0x000C0000) /* PINSEL0 Mask for UART1 RX only */
 
#define U1RBR   UART1_BASE->rbr /* Receive Buffer Register */
 
#define U1THR   UART1_BASE->thr /* Transmit Holding Register */
 
#define U1IER   UART1_BASE->ier /* Interrupt Enable Register */
 
#define U1IIR   UART1_BASE->iir /* Interrupt ID Register */
 
#define U1FCR   UART1_BASE->fcr /* FIFO Control Register */
 
#define U1LCR   UART1_BASE->lcr /* Line Control Register */
 
#define U1MCR   UART1_BASE->mcr /* MODEM Control Register */
 
#define U1LSR   UART1_BASE->lsr /* Line Status Register */
 
#define U1MSR   UART1_BASE->msr /* MODEM Status Register */
 
#define U1SCR   UART1_BASE->scr /* Scratch Pad Register */
 
#define U1DLL   UART1_BASE->dll /* Divisor Latch Register (LSB) */
 
#define U1DLM   UART1_BASE->dlm /* Divisor Latch Register (MSB) */
 
#define I2C0   ((i2cRegs_t *)0xE001C000)
 
#define I2C0CONSET   I2C0->conset /* Control Set Register */
 
#define I2C0STAT   I2C0->stat /* Status Register */
 
#define I2C0DAT   I2C0->dat /* Data Register */
 
#define I2C0ADR   I2C0->adr /* Slave Address Register */
 
#define I2C0SCLH   I2C0->sclh /* SCL Duty Cycle Register (high half word) */
 
#define I2C0SCLL   I2C0->scll /* SCL Duty Cycle Register (low half word) */
 
#define I2C0CONCLR   I2C0->conclr /* Control Clear Register */
 
#define I2C1   ((i2cRegs_t *)0xE005C000)
 
#define I2C1CONSET   I2C1->conset /* Control Set Register */
 
#define I2C1STAT   I2C1->stat /* Status Register */
 
#define I2C1DAT   I2C1->dat /* Data Register */
 
#define I2C1ADR   I2C1->adr /* Slave Address Register */
 
#define I2C1SCLH   I2C1->sclh /* SCL Duty Cycle Register (high half word) */
 
#define I2C1SCLL   I2C1->scll /* SCL Duty Cycle Register (low half word) */
 
#define I2C1CONCLR   I2C1->conclr /* Control Clear Register */
 
#define AA   2
 
#define SI   3
 
#define STO   4
 
#define STA   5
 
#define I2EN   6
 
#define AAC   2
 
#define SIC   3
 
#define STAC   5
 
#define I2ENC   6
 
#define SPI0   ((spiRegs_t *)0xE0020000)
 
#define S0SPCR   SPI0->cr /* Control Register */
 
#define S0SPSR   SPI0->sr /* Status Register */
 
#define S0SPDR   SPI0->dr /* Data Register */
 
#define S0SPCCR   SPI0->ccr /* Clock Counter Register */
 
#define S0SPINT   SPI0->flag /* Interrupt Flag Register */
 
#define SPI0IF   0
 
#define SPI1   ((sspRegs_t *)0xE0068000)
 
#define SPI1IF   0
 
#define SSPCR0   SPI1->cr0 /* Control Register 0 */
 
#define SSPCR1   SPI1->cr1 /* Control Register 1 */
 
#define SSPDR   SPI1->dr /* Data register */
 
#define SSPSR   SPI1->sr /* Status register */
 
#define SSPCPSR   SPI1->cpsr /* Clock prescale register */
 
#define SSPIMSC   SPI1->imsc /* Interrupt mask register */
 
#define SSPRIS   SPI1->ris /* Raw interrupt status register */
 
#define SSPMIS   SPI1->mis /* Masked interrupt status register */
 
#define SSPICR   SPI1->icr /* Interrupt clear register */
 
#define DSS   0
 
#define FRF   4
 
#define CPOL   6
 
#define CPHA   7
 
#define SCR   8
 
#define DSS_VAL4   0x3
 
#define DSS_VAL5   0x4
 
#define DSS_VAL6   0x5
 
#define DSS_VAL7   0x6
 
#define DSS_VAL8   0x7
 
#define DSS_VAL9   0x8
 
#define DSS_VAL10   0x9
 
#define DSS_VAL11   0xA
 
#define DSS_VAL12   0xB
 
#define DSS_VAL13   0XC
 
#define DSS_VAL14   0xD
 
#define DSS_VAL15   0xE
 
#define DSS_VAL16   0xF
 
#define LBM   0
 
#define SSE   1
 
#define MS   2
 
#define SOD   3
 
#define RORIM   0
 
#define RTIM   1
 
#define RXIM   2
 
#define TXIM   3
 
#define TFE   0
 
#define TNF   1
 
#define RNE   2
 
#define RFF   3
 
#define BSY   4
 
#define RORMIS   0
 
#define RTMIS   1
 
#define RXMIS   2
 
#define TXMIS   3
 
#define RORIC   0
 
#define RTIC   1
 
#define RTC   ((rtcRegs_t *)0xE0024000)
 
#define RTCILR   RTC->ilr /* Interrupt Location Register */
 
#define RTCCTC   RTC->ctc /* Clock Tick Counter */
 
#define RTCCCR   RTC->ccr /* Clock Control Register */
 
#define RTCCIIR   RTC->ciir /* Counter Increment Interrupt Register */
 
#define RTCAMR   RTC->amr /* Alarm Mask Register */
 
#define RTCCTIME0   RTC->ctime0 /* Consolidated Time Register 0 */
 
#define RTCCTIME1   RTC->ctime1 /* Consolidated Time Register 1 */
 
#define RTCCTIME2   RTC->ctime2 /* Consolidated Time Register 2 */
 
#define RTCSEC   RTC->sec /* Seconds Register */
 
#define RTCMIN   RTC->min /* Minutes Register */
 
#define RTCHOUR   RTC->hour /* Hours Register */
 
#define RTCDOM   RTC->dom /* Day Of Month Register */
 
#define RTCDOW   RTC->dow /* Day Of Week Register */
 
#define RTCDOY   RTC->doy /* Day Of Year Register */
 
#define RTCMONTH   RTC->month /* Months Register */
 
#define RTCYEAR   RTC->year /* Years Register */
 
#define RTCALSEC   RTC->alsec /* Alarm Seconds Register */
 
#define RTCALMIN   RTC->almin /* Alarm Minutes Register */
 
#define RTCALHOUR   RTC->alhour /* Alarm Hours Register */
 
#define RTCALDOM   RTC->aldom /* Alarm Day Of Month Register */
 
#define RTCALDOW   RTC->aldow /* Alarm Day Of Week Register */
 
#define RTCALDOY   RTC->aldoy /* Alarm Day Of Year Register */
 
#define RTCALMON   RTC->almon /* Alarm Months Register */
 
#define RTCALYEAR   RTC->alyear /* Alarm Years Register */
 
#define RTCPREINT   RTC->preint /* Prescale Value Register (integer) */
 
#define RTCPREFRAC   RTC->prefrac /* Prescale Value Register (fraction) */
 
#define GPIO   ((gpioRegs_t *)0xE0028000)
 
#define IO0PIN   GPIO->in0 /* P0 Pin Value Register */
 
#define IO0SET   GPIO->set0 /* P0 Pin Output Set Register */
 
#define IO0DIR   GPIO->dir0 /* P0 Pin Direction Register */
 
#define IO0CLR   GPIO->clr0 /* P0 Pin Output Clear Register */
 
#define IO1PIN   GPIO->in1 /* P1 Pin Value Register */
 
#define IO1SET   GPIO->set1 /* P1 Pin Output Set Register */
 
#define IO1DIR   GPIO->dir1 /* P1 Pin Direction Register */
 
#define IO1CLR   GPIO->clr1 /* P1 Pin Output Clear Register */
 
#define PINSEL   ((pinRegs_t *)0xE002C000)
 
#define PINSEL0   PINSEL->sel0 /* Pin Function Select Register 0 */
 
#define PINSEL1   PINSEL->sel1 /* Pin Function Select Register 1 */
 
#define PINSEL2   PINSEL->sel2 /* Pin Function Select Register 2 */
 
#define ADC0   ((adcRegs_t *)0xE0034000)
 
#define AD0CR   ADC0->cr /* Control Register */
 
#define AD0GDR   ADC0->gdr /* Global Data Register */
 
#define ADGSR   ADC0->gsr /* ADC global start resister */
 
#define AD0INTEN   ADC0->inten /* Interrupt Enable Register */
 
#define AD0DR0   ADC0->dr0 /* Channel 0 Data Register */
 
#define AD0DR1   ADC0->dr1 /* Channel 1 Data Register */
 
#define AD0DR2   ADC0->dr2 /* Channel 2 Data Register */
 
#define AD0DR3   ADC0->dr3 /* Channel 3 Data Register */
 
#define AD0DR4   ADC0->dr4 /* Channel 4 Data Register */
 
#define AD0DR5   ADC0->dr5 /* Channel 5 Data Register */
 
#define AD0DR6   ADC0->dr6 /* Channel 6 Data Register */
 
#define AD0DR7   ADC0->dr7 /* Channel 7 Data Register */
 
#define AD0STAT   ADC0->stat /* Status Register */
 
#define ADC1   ((adcRegs_t *)0xE0060000)
 
#define AD1CR   ADC1->cr /* Control Register */
 
#define AD1GDR   ADC1->gdr /* Data Register */
 
#define AD1INTEN   ADC1->inten /* Interrupt Enable Register */
 
#define AD1DR0   ADC1->dr0 /* Channel 0 Data Register */
 
#define AD1DR1   ADC1->dr1 /* Channel 1 Data Register */
 
#define AD1DR2   ADC1->dr2 /* Channel 2 Data Register */
 
#define AD1DR3   ADC1->dr3 /* Channel 3 Data Register */
 
#define AD1DR4   ADC1->dr4 /* Channel 4 Data Register */
 
#define AD1DR5   ADC1->dr5 /* Channel 5 Data Register */
 
#define AD1DR6   ADC1->dr6 /* Channel 6 Data Register */
 
#define AD1DR7   ADC1->dr7 /* Channel 7 Data Register */
 
#define AD1STAT   ADC1->stat /* Status Register */
 
#define DACR   (*(REG32*) 0xE006C000)
 
#define SCB   ((scbRegs_t *)0xE01FC000)
 
#define MAMCR   SCB->mam.cr /* Control Register */
 
#define MAMTIM   SCB->mam.tim /* Timing Control Register */
 
#define MEMMAP   SCB->memmap
 
#define PLLCON   SCB->pll.con /* Control Register */
 
#define PLLCFG   SCB->pll.cfg /* Configuration Register */
 
#define PLLSTAT   SCB->pll.stat /* Status Register */
 
#define PLLFEED   SCB->pll.feed /* Feed Register */
 
#define PCON   SCB->p.con /* Control Register */
 
#define PCONP   SCB->p.conp /* Peripherals Register */
 
#define VPBDIV   SCB->vpbdiv
 
#define EXTINT   SCB->ext.flag /* Flag Register */
 
#define EXTWAKE   SCB->ext.wake /* Wakeup Register */
 
#define EXTMODE   SCB->ext.mode /* Mode Register */
 
#define EXTPOLAR   SCB->ext.polar /* Polarity Register */
 
#define VIC   ((vicRegs_t *)0xFFFFF000)
 
#define VICIRQStatus   VIC->irqStatus /* IRQ Status Register */
 
#define VICFIQStatus   VIC->fiqStatus /* FIQ Status Register */
 
#define VICRawIntr   VIC->rawIntr /* Raw Interrupt Status Register */
 
#define VICIntSelect   VIC->intSelect /* Interrupt Select Register */
 
#define VICIntEnable   VIC->intEnable /* Interrupt Enable Register */
 
#define VICIntEnClear   VIC->intEnClear /* Interrupt Enable Clear Register */
 
#define VICSoftInt   VIC->softInt /* Software Interrupt Register */
 
#define VICSoftIntClear   VIC->softIntClear /* Software Interrupt Clear Register */
 
#define VICProtection   VIC->protection /* Protection Enable Register */
 
#define VICVectAddr   VIC->vectAddr /* Vector Address Register */
 
#define VICDefVectAddr   VIC->defVectAddr /* Default Vector Address Register */
 
#define VICVectAddr0   VIC->vectAddr0 /* Vector Address 0 Register */
 
#define VICVectAddr1   VIC->vectAddr1 /* Vector Address 1 Register */
 
#define VICVectAddr2   VIC->vectAddr2 /* Vector Address 2 Register */
 
#define VICVectAddr3   VIC->vectAddr3 /* Vector Address 3 Register */
 
#define VICVectAddr4   VIC->vectAddr4 /* Vector Address 4 Register */
 
#define VICVectAddr5   VIC->vectAddr5 /* Vector Address 5 Register */
 
#define VICVectAddr6   VIC->vectAddr6 /* Vector Address 6 Register */
 
#define VICVectAddr7   VIC->vectAddr7 /* Vector Address 7 Register */
 
#define VICVectAddr8   VIC->vectAddr8 /* Vector Address 8 Register */
 
#define VICVectAddr9   VIC->vectAddr9 /* Vector Address 9 Register */
 
#define VICVectAddr10   VIC->vectAddr10 /* Vector Address 10 Register */
 
#define VICVectAddr11   VIC->vectAddr11 /* Vector Address 11 Register */
 
#define VICVectAddr12   VIC->vectAddr12 /* Vector Address 12 Register */
 
#define VICVectAddr13   VIC->vectAddr13 /* Vector Address 13 Register */
 
#define VICVectAddr14   VIC->vectAddr14 /* Vector Address 14 Register */
 
#define VICVectAddr15   VIC->vectAddr15 /* Vector Address 15 Register */
 
#define VICVectCntl0   VIC->vectCntl0 /* Vector Control 0 Register */
 
#define VICVectCntl1   VIC->vectCntl1 /* Vector Control 1 Register */
 
#define VICVectCntl2   VIC->vectCntl2 /* Vector Control 2 Register */
 
#define VICVectCntl3   VIC->vectCntl3 /* Vector Control 3 Register */
 
#define VICVectCntl4   VIC->vectCntl4 /* Vector Control 4 Register */
 
#define VICVectCntl5   VIC->vectCntl5 /* Vector Control 5 Register */
 
#define VICVectCntl6   VIC->vectCntl6 /* Vector Control 6 Register */
 
#define VICVectCntl7   VIC->vectCntl7 /* Vector Control 7 Register */
 
#define VICVectCntl8   VIC->vectCntl8 /* Vector Control 8 Register */
 
#define VICVectCntl9   VIC->vectCntl9 /* Vector Control 9 Register */
 
#define VICVectCntl10   VIC->vectCntl10 /* Vector Control 10 Register */
 
#define VICVectCntl11   VIC->vectCntl11 /* Vector Control 11 Register */
 
#define VICVectCntl12   VIC->vectCntl12 /* Vector Control 12 Register */
 
#define VICVectCntl13   VIC->vectCntl13 /* Vector Control 13 Register */
 
#define VICVectCntl14   VIC->vectCntl14 /* Vector Control 14 Register */
 
#define VICVectCntl15   VIC->vectCntl15 /* Vector Control 15 Register */
 
#define CAN_CENTRAL   ((can_central_Regs_t *)0xE0040000)
 
#define CANTxSR   CAN_CENTRAL->tx_sr /* CAN Central Transmit Status Register */
 
#define CANRxSR   CAN_CENTRAL->rx_sr /* CAN Central Receive Status Register */
 
#define CANMSR   CAN_CENTRAL->m_sr /* CAN Central Miscellanous Register */
 
#define CAN_ACCEPT   ((can_accept_Regs_t *)0xE003C000)
 
#define AFMR   CAN_ACCEPT->afmr /* Acceptance Filter Register */
 
#define CAN1   ((can_Regs_t *)0xE0044000)
 
#define C1MOD   CAN1->can_mod /* */
 
#define C1CMR   CAN1->can_cmr /* */
 
#define C1GSR   CAN1->can_gsr /* */
 
#define C1ICR   CAN1->can_icr
 
#define C1IER   CAN1->can_ier
 
#define C1BTR   CAN1->can_btr
 
#define C1EWL   CAN1->can_ewl
 
#define C1SR   CAN1->can_sr
 
#define C1RFS   CAN1->can_rfs
 
#define C1RID   CAN1->can_rid
 
#define C1RDA   CAN1->can_rda
 
#define C1RDB   CAN1->can_rdb
 
#define C1TFI1   CAN1->can_tfi1
 
#define C1TID1   CAN1->can_tid1
 
#define C1TDA1   CAN1->can_tda1
 
#define C1TDB1   CAN1->can_tdb1
 
#define C1TFI2   CAN1->can_tfi2
 
#define C1TID2   CAN1->can_tid2
 
#define C1TDA2   CAN1->can_tda2
 
#define C1TDB2   CAN1->can_tdb2
 
#define C1TFI3   CAN1->can_tfi3
 
#define C1TID3   CAN1->can_tid3
 
#define C1TDA3   CAN1->can_tda3
 
#define C1TDB3   CAN1->can_tdb3
 
#define CAN2   ((can_Regs_t *)0xE0048000)
 
#define C2MOD   CAN2->can_mod /* */
 
#define C2CMR   CAN2->can_cmr /* */
 
#define C2GSR   CAN2->can_gsr /* */
 
#define C2ICR   CAN2->can_icr
 
#define C2IER   CAN2->can_ier
 
#define C2BTR   CAN2->can_btr
 
#define C2EWL   CAN2->can_ewl
 
#define C2SR   CAN2->can_sr
 
#define C2RFS   CAN2->can_rfs
 
#define C2RID   CAN2->can_rid
 
#define C2RDA   CAN2->can_rda
 
#define C2RDB   CAN2->can_rdb
 
#define C2TFI1   CAN2->can_tfi1
 
#define C2TID1   CAN2->can_tid1
 
#define C2TDA1   CAN2->can_tda1
 
#define C2TDB1   CAN2->can_tdb1
 
#define C2TFI2   CAN2->can_tfi2
 
#define C2TID2   CAN2->can_tid2
 
#define C2TDA2   CAN2->can_tda2
 
#define C2TDB2   CAN2->can_tdb2
 
#define C2TFI3   CAN2->can_tfi3
 
#define C2TID3   CAN2->can_tid3
 
#define C2TDA3   CAN2->can_tda3
 
#define C2TDB3   CAN2->can_tdb3
 

Macro Definition Documentation

#define AA   2
#define AAC   2

Definition at line 187 of file LPC21xx.h.

Referenced by I2cReceive().

#define AD0CR   ADC0->cr /* Control Register */

Definition at line 356 of file LPC21xx.h.

Referenced by adc_init().

#define AD0DR0   ADC0->dr0 /* Channel 0 Data Register */

Definition at line 360 of file LPC21xx.h.

#define AD0DR1   ADC0->dr1 /* Channel 1 Data Register */

Definition at line 361 of file LPC21xx.h.

#define AD0DR2   ADC0->dr2 /* Channel 2 Data Register */

Definition at line 362 of file LPC21xx.h.

#define AD0DR3   ADC0->dr3 /* Channel 3 Data Register */

Definition at line 363 of file LPC21xx.h.

#define AD0DR4   ADC0->dr4 /* Channel 4 Data Register */

Definition at line 364 of file LPC21xx.h.

#define AD0DR5   ADC0->dr5 /* Channel 5 Data Register */

Definition at line 365 of file LPC21xx.h.

#define AD0DR6   ADC0->dr6 /* Channel 6 Data Register */

Definition at line 366 of file LPC21xx.h.

#define AD0DR7   ADC0->dr7 /* Channel 7 Data Register */

Definition at line 367 of file LPC21xx.h.

#define AD0GDR   ADC0->gdr /* Global Data Register */

Definition at line 357 of file LPC21xx.h.

Referenced by adcISR0().

#define AD0INTEN   ADC0->inten /* Interrupt Enable Register */

Definition at line 359 of file LPC21xx.h.

#define AD0STAT   ADC0->stat /* Status Register */

Definition at line 368 of file LPC21xx.h.

#define AD1CR   ADC1->cr /* Control Register */

Definition at line 373 of file LPC21xx.h.

Referenced by adc_init().

#define AD1DR0   ADC1->dr0 /* Channel 0 Data Register */

Definition at line 376 of file LPC21xx.h.

#define AD1DR1   ADC1->dr1 /* Channel 1 Data Register */

Definition at line 377 of file LPC21xx.h.

#define AD1DR2   ADC1->dr2 /* Channel 2 Data Register */

Definition at line 378 of file LPC21xx.h.

#define AD1DR3   ADC1->dr3 /* Channel 3 Data Register */

Definition at line 379 of file LPC21xx.h.

#define AD1DR4   ADC1->dr4 /* Channel 4 Data Register */

Definition at line 380 of file LPC21xx.h.

#define AD1DR5   ADC1->dr5 /* Channel 5 Data Register */

Definition at line 381 of file LPC21xx.h.

#define AD1DR6   ADC1->dr6 /* Channel 6 Data Register */

Definition at line 382 of file LPC21xx.h.

#define AD1DR7   ADC1->dr7 /* Channel 7 Data Register */

Definition at line 383 of file LPC21xx.h.

#define AD1GDR   ADC1->gdr /* Data Register */

Definition at line 374 of file LPC21xx.h.

Referenced by adcISR1().

#define AD1INTEN   ADC1->inten /* Interrupt Enable Register */

Definition at line 375 of file LPC21xx.h.

#define AD1STAT   ADC1->stat /* Status Register */

Definition at line 384 of file LPC21xx.h.

#define ADC0   ((adcRegs_t *)0xE0034000)

Definition at line 353 of file LPC21xx.h.

#define ADC1   ((adcRegs_t *)0xE0060000)

Definition at line 370 of file LPC21xx.h.

Referenced by adc_init().

#define ADGSR   ADC0->gsr /* ADC global start resister */

Definition at line 358 of file LPC21xx.h.

#define AFMR   CAN_ACCEPT->afmr /* Acceptance Filter Register */

Definition at line 482 of file LPC21xx.h.

#define BSY   4

Definition at line 281 of file LPC21xx.h.

Referenced by SpiAutomaton().

#define C1BTR   CAN1->can_btr

Definition at line 490 of file LPC21xx.h.

#define C1CMR   CAN1->can_cmr /* */

Definition at line 486 of file LPC21xx.h.

#define C1EWL   CAN1->can_ewl

Definition at line 491 of file LPC21xx.h.

#define C1GSR   CAN1->can_gsr /* */

Definition at line 487 of file LPC21xx.h.

#define C1ICR   CAN1->can_icr

Definition at line 488 of file LPC21xx.h.

#define C1IER   CAN1->can_ier

Definition at line 489 of file LPC21xx.h.

#define C1MOD   CAN1->can_mod /* */

Definition at line 485 of file LPC21xx.h.

#define C1RDA   CAN1->can_rda

Definition at line 495 of file LPC21xx.h.

#define C1RDB   CAN1->can_rdb

Definition at line 496 of file LPC21xx.h.

#define C1RFS   CAN1->can_rfs

Definition at line 493 of file LPC21xx.h.

#define C1RID   CAN1->can_rid

Definition at line 494 of file LPC21xx.h.

#define C1SR   CAN1->can_sr

Definition at line 492 of file LPC21xx.h.

#define C1TDA1   CAN1->can_tda1

Definition at line 499 of file LPC21xx.h.

#define C1TDA2   CAN1->can_tda2

Definition at line 503 of file LPC21xx.h.

#define C1TDA3   CAN1->can_tda3

Definition at line 507 of file LPC21xx.h.

#define C1TDB1   CAN1->can_tdb1

Definition at line 500 of file LPC21xx.h.

#define C1TDB2   CAN1->can_tdb2

Definition at line 504 of file LPC21xx.h.

#define C1TDB3   CAN1->can_tdb3

Definition at line 508 of file LPC21xx.h.

#define C1TFI1   CAN1->can_tfi1

Definition at line 497 of file LPC21xx.h.

#define C1TFI2   CAN1->can_tfi2

Definition at line 501 of file LPC21xx.h.

#define C1TFI3   CAN1->can_tfi3

Definition at line 505 of file LPC21xx.h.

#define C1TID1   CAN1->can_tid1

Definition at line 498 of file LPC21xx.h.

#define C1TID2   CAN1->can_tid2

Definition at line 502 of file LPC21xx.h.

#define C1TID3   CAN1->can_tid3

Definition at line 506 of file LPC21xx.h.

#define C2BTR   CAN2->can_btr

Definition at line 516 of file LPC21xx.h.

#define C2CMR   CAN2->can_cmr /* */

Definition at line 512 of file LPC21xx.h.

#define C2EWL   CAN2->can_ewl

Definition at line 517 of file LPC21xx.h.

#define C2GSR   CAN2->can_gsr /* */

Definition at line 513 of file LPC21xx.h.

#define C2ICR   CAN2->can_icr

Definition at line 514 of file LPC21xx.h.

#define C2IER   CAN2->can_ier

Definition at line 515 of file LPC21xx.h.

#define C2MOD   CAN2->can_mod /* */

Definition at line 511 of file LPC21xx.h.

#define C2RDA   CAN2->can_rda

Definition at line 521 of file LPC21xx.h.

#define C2RDB   CAN2->can_rdb

Definition at line 522 of file LPC21xx.h.

#define C2RFS   CAN2->can_rfs

Definition at line 519 of file LPC21xx.h.

#define C2RID   CAN2->can_rid

Definition at line 520 of file LPC21xx.h.

#define C2SR   CAN2->can_sr

Definition at line 518 of file LPC21xx.h.

#define C2TDA1   CAN2->can_tda1

Definition at line 525 of file LPC21xx.h.

#define C2TDA2   CAN2->can_tda2

Definition at line 529 of file LPC21xx.h.

#define C2TDA3   CAN2->can_tda3

Definition at line 533 of file LPC21xx.h.

#define C2TDB1   CAN2->can_tdb1

Definition at line 526 of file LPC21xx.h.

#define C2TDB2   CAN2->can_tdb2

Definition at line 530 of file LPC21xx.h.

#define C2TDB3   CAN2->can_tdb3

Definition at line 534 of file LPC21xx.h.

#define C2TFI1   CAN2->can_tfi1

Definition at line 523 of file LPC21xx.h.

#define C2TFI2   CAN2->can_tfi2

Definition at line 527 of file LPC21xx.h.

#define C2TFI3   CAN2->can_tfi3

Definition at line 531 of file LPC21xx.h.

#define C2TID1   CAN2->can_tid1

Definition at line 524 of file LPC21xx.h.

#define C2TID2   CAN2->can_tid2

Definition at line 528 of file LPC21xx.h.

#define C2TID3   CAN2->can_tid3

Definition at line 532 of file LPC21xx.h.

#define CAN1   ((can_Regs_t *)0xE0044000)

Definition at line 484 of file LPC21xx.h.

Referenced by can_hw_init(), and can_hw_transmit().

#define CAN2   ((can_Regs_t *)0xE0048000)

Definition at line 510 of file LPC21xx.h.

#define CAN_ACCEPT   ((can_accept_Regs_t *)0xE003C000)

Definition at line 481 of file LPC21xx.h.

#define CAN_CENTRAL   ((can_central_Regs_t *)0xE0040000)

Definition at line 476 of file LPC21xx.h.

#define CANMSR   CAN_CENTRAL->m_sr /* CAN Central Miscellanous Register */

Definition at line 479 of file LPC21xx.h.

#define CANRxSR   CAN_CENTRAL->rx_sr /* CAN Central Receive Status Register */

Definition at line 478 of file LPC21xx.h.

#define CANTxSR   CAN_CENTRAL->tx_sr /* CAN Central Transmit Status Register */

Definition at line 477 of file LPC21xx.h.

#define CPHA   7

Definition at line 246 of file LPC21xx.h.

Referenced by SpiClearCPHA(), and SpiSetCPHA().

#define CPOL   6

Definition at line 245 of file LPC21xx.h.

Referenced by SpiClearCPOL().

#define DACR   (*(REG32*) 0xE006C000)

Definition at line 389 of file LPC21xx.h.

Referenced by DACSet().

#define DSS   0

Definition at line 243 of file LPC21xx.h.

Referenced by SpiSetDataSize().

#define DSS_VAL10   0x9

Definition at line 256 of file LPC21xx.h.

#define DSS_VAL11   0xA

Definition at line 257 of file LPC21xx.h.

#define DSS_VAL12   0xB

Definition at line 258 of file LPC21xx.h.

#define DSS_VAL13   0XC

Definition at line 259 of file LPC21xx.h.

#define DSS_VAL14   0xD

Definition at line 260 of file LPC21xx.h.

#define DSS_VAL15   0xE

Definition at line 261 of file LPC21xx.h.

#define DSS_VAL16   0xF

Definition at line 262 of file LPC21xx.h.

Referenced by SpiSetDataSize().

#define DSS_VAL4   0x3

Definition at line 250 of file LPC21xx.h.

#define DSS_VAL5   0x4

Definition at line 251 of file LPC21xx.h.

#define DSS_VAL6   0x5

Definition at line 252 of file LPC21xx.h.

#define DSS_VAL7   0x6

Definition at line 253 of file LPC21xx.h.

#define DSS_VAL8   0x7

Definition at line 254 of file LPC21xx.h.

Referenced by SpiSetDataSize().

#define DSS_VAL9   0x8

Definition at line 255 of file LPC21xx.h.

#define EXTINT   SCB->ext.flag /* Flag Register */
#define EXTMODE   SCB->ext.mode /* Mode Register */
#define EXTPOLAR   SCB->ext.polar /* Polarity Register */
#define EXTWAKE   SCB->ext.wake /* Wakeup Register */

Definition at line 418 of file LPC21xx.h.

#define FRF   4

Definition at line 244 of file LPC21xx.h.

#define GPIO   ((gpioRegs_t *)0xE0028000)

Definition at line 330 of file LPC21xx.h.

#define I2C0   ((i2cRegs_t *)0xE001C000)

Definition at line 154 of file LPC21xx.h.

#define I2C0ADR   I2C0->adr /* Slave Address Register */

Definition at line 160 of file LPC21xx.h.

#define I2C0CONCLR   I2C0->conclr /* Control Clear Register */

Definition at line 163 of file LPC21xx.h.

#define I2C0CONSET   I2C0->conset /* Control Set Register */

Definition at line 157 of file LPC21xx.h.

#define I2C0DAT   I2C0->dat /* Data Register */

Definition at line 159 of file LPC21xx.h.

#define I2C0SCLH   I2C0->sclh /* SCL Duty Cycle Register (high half word) */

Definition at line 161 of file LPC21xx.h.

#define I2C0SCLL   I2C0->scll /* SCL Duty Cycle Register (low half word) */

Definition at line 162 of file LPC21xx.h.

#define I2C0STAT   I2C0->stat /* Status Register */

Definition at line 158 of file LPC21xx.h.

#define I2C1   ((i2cRegs_t *)0xE005C000)

Definition at line 166 of file LPC21xx.h.

#define I2C1ADR   I2C1->adr /* Slave Address Register */

Definition at line 171 of file LPC21xx.h.

#define I2C1CONCLR   I2C1->conclr /* Control Clear Register */

Definition at line 174 of file LPC21xx.h.

#define I2C1CONSET   I2C1->conset /* Control Set Register */

Definition at line 168 of file LPC21xx.h.

#define I2C1DAT   I2C1->dat /* Data Register */

Definition at line 170 of file LPC21xx.h.

#define I2C1SCLH   I2C1->sclh /* SCL Duty Cycle Register (high half word) */

Definition at line 172 of file LPC21xx.h.

#define I2C1SCLL   I2C1->scll /* SCL Duty Cycle Register (low half word) */

Definition at line 173 of file LPC21xx.h.

#define I2C1STAT   I2C1->stat /* Status Register */

Definition at line 169 of file LPC21xx.h.

#define I2EN   6

Definition at line 183 of file LPC21xx.h.

#define I2ENC   6

Definition at line 190 of file LPC21xx.h.

#define IO0CLR   GPIO->clr0 /* P0 Pin Output Clear Register */

Definition at line 336 of file LPC21xx.h.

Referenced by gpio_clear(), gpio_toggle(), and main().

#define IO0DIR   GPIO->dir0 /* P0 Pin Direction Register */
#define IO0PIN   GPIO->in0 /* P0 Pin Value Register */

Definition at line 333 of file LPC21xx.h.

Referenced by gpio_get(), gpio_toggle(), and main().

#define IO0SET   GPIO->set0 /* P0 Pin Output Set Register */

Definition at line 334 of file LPC21xx.h.

Referenced by gpio_set(), gpio_toggle(), and main().

#define IO1CLR   GPIO->clr1 /* P1 Pin Output Clear Register */

Definition at line 340 of file LPC21xx.h.

Referenced by gpio_clear(), gpio_toggle(), and PWM_ISR().

#define IO1DIR   GPIO->dir1 /* P1 Pin Direction Register */
#define IO1PIN   GPIO->in1 /* P1 Pin Value Register */

Definition at line 337 of file LPC21xx.h.

Referenced by gpio_get(), and gpio_toggle().

#define IO1SET   GPIO->set1 /* P1 Pin Output Set Register */

Definition at line 338 of file LPC21xx.h.

Referenced by actuators_4015_init(), actuators_4017_init(), gpio_set(), gpio_toggle(), and PWM_ISR().

#define LBM   0

Definition at line 265 of file LPC21xx.h.

#define MAMCR   SCB->mam.cr /* Control Register */

Definition at line 397 of file LPC21xx.h.

Referenced by mcu_arch_init().

#define MAMTIM   SCB->mam.tim /* Timing Control Register */

Definition at line 398 of file LPC21xx.h.

Referenced by mcu_arch_init().

#define MEMMAP   SCB->memmap

Definition at line 401 of file LPC21xx.h.

Referenced by mcu_arch_init().

#define MS   2

Definition at line 267 of file LPC21xx.h.

#define PCON   SCB->p.con /* Control Register */

Definition at line 410 of file LPC21xx.h.

#define PCONP   SCB->p.conp /* Peripherals Register */

Definition at line 411 of file LPC21xx.h.

#define PINSEL   ((pinRegs_t *)0xE002C000)

Definition at line 344 of file LPC21xx.h.

#define PINSEL0   PINSEL->sel0 /* Pin Function Select Register 0 */

Definition at line 347 of file LPC21xx.h.

Referenced by adc_init(), and baro_MS5534A_init().

#define PINSEL1   PINSEL->sel1 /* Pin Function Select Register 1 */
#define PINSEL2   PINSEL->sel2 /* Pin Function Select Register 2 */

Definition at line 349 of file LPC21xx.h.

Referenced by actuators_4015_init(), and actuators_4017_init().

#define PLLCFG   SCB->pll.cfg /* Configuration Register */

Definition at line 405 of file LPC21xx.h.

Referenced by mcu_arch_init().

#define PLLCON   SCB->pll.con /* Control Register */

Definition at line 404 of file LPC21xx.h.

Referenced by mcu_arch_init().

#define PLLFEED   SCB->pll.feed /* Feed Register */

Definition at line 407 of file LPC21xx.h.

Referenced by mcu_arch_init().

#define PLLSTAT   SCB->pll.stat /* Status Register */

Definition at line 406 of file LPC21xx.h.

Referenced by mcu_arch_init().

#define PWM   ((pwmTmrRegs_t *)0xE0014000)

Definition at line 91 of file LPC21xx.h.

#define PWMIR   PWM->ir /* Interrupt Register */

Definition at line 94 of file LPC21xx.h.

Referenced by PWM_ISR().

#define PWMLER   PWM->ler /* Latch Enable Register */
#define PWMMCR   PWM->mcr /* Match Control Register */

Definition at line 99 of file LPC21xx.h.

Referenced by actuators_4015_init(), and PWM_ISR().

#define PWMMR0   PWM->mr0 /* Match Register 0 */
#define PWMMR1   PWM->mr1 /* Match Register 1 */

Definition at line 101 of file LPC21xx.h.

#define PWMMR2   PWM->mr2 /* Match Register 2 */

Definition at line 102 of file LPC21xx.h.

Referenced by baro_MS5534A_init().

#define PWMMR3   PWM->mr3 /* Match Register 3 */

Definition at line 103 of file LPC21xx.h.

#define PWMMR4   PWM->mr4 /* Match Register 4 */

Definition at line 104 of file LPC21xx.h.

#define PWMMR5   PWM->mr5 /* Match Register 5 */

Definition at line 105 of file LPC21xx.h.

#define PWMMR6   PWM->mr6 /* Match Register 6 */

Definition at line 106 of file LPC21xx.h.

#define PWMPC   PWM->pc /* Prescale Counter Register */

Definition at line 98 of file LPC21xx.h.

#define PWMPCR   PWM->pcr /* Control Register */

Definition at line 107 of file LPC21xx.h.

Referenced by actuators_4015_init(), actuators_pwm_arch_init(), and baro_MS5534A_init().

#define PWMPR   PWM->pr /* Prescale Register */

Definition at line 97 of file LPC21xx.h.

Referenced by actuators_4015_init(), actuators_pwm_arch_init(), and baro_MS5534A_init().

#define PWMTC   PWM->tc /* Timer Counter */

Definition at line 96 of file LPC21xx.h.

#define PWMTCR   PWM->tcr /* Timer Control Register */

Definition at line 95 of file LPC21xx.h.

Referenced by actuators_4015_init(), actuators_pwm_arch_init(), and baro_MS5534A_init().

#define REG16   volatile unsigned short

Definition at line 19 of file LPC21xx.h.

#define REG32   volatile unsigned long

Definition at line 20 of file LPC21xx.h.

#define REG_8   volatile unsigned char

Definition at line 18 of file LPC21xx.h.

#define RFF   3

Definition at line 280 of file LPC21xx.h.

#define RNE   2

Definition at line 279 of file LPC21xx.h.

Referenced by SPI1_ISR(), and SpiReceive().

#define RORIC   0

Definition at line 290 of file LPC21xx.h.

#define RORIM   0

Definition at line 271 of file LPC21xx.h.

#define RORMIS   0

Definition at line 284 of file LPC21xx.h.

#define RTC   ((rtcRegs_t *)0xE0024000)

Definition at line 298 of file LPC21xx.h.

#define RTCALDOM   RTC->aldom /* Alarm Day Of Month Register */

Definition at line 320 of file LPC21xx.h.

#define RTCALDOW   RTC->aldow /* Alarm Day Of Week Register */

Definition at line 321 of file LPC21xx.h.

#define RTCALDOY   RTC->aldoy /* Alarm Day Of Year Register */

Definition at line 322 of file LPC21xx.h.

#define RTCALHOUR   RTC->alhour /* Alarm Hours Register */

Definition at line 319 of file LPC21xx.h.

#define RTCALMIN   RTC->almin /* Alarm Minutes Register */

Definition at line 318 of file LPC21xx.h.

#define RTCALMON   RTC->almon /* Alarm Months Register */

Definition at line 323 of file LPC21xx.h.

#define RTCALSEC   RTC->alsec /* Alarm Seconds Register */

Definition at line 317 of file LPC21xx.h.

#define RTCALYEAR   RTC->alyear /* Alarm Years Register */

Definition at line 324 of file LPC21xx.h.

#define RTCAMR   RTC->amr /* Alarm Mask Register */

Definition at line 305 of file LPC21xx.h.

#define RTCCCR   RTC->ccr /* Clock Control Register */

Definition at line 303 of file LPC21xx.h.

#define RTCCIIR   RTC->ciir /* Counter Increment Interrupt Register */

Definition at line 304 of file LPC21xx.h.

#define RTCCTC   RTC->ctc /* Clock Tick Counter */

Definition at line 302 of file LPC21xx.h.

#define RTCCTIME0   RTC->ctime0 /* Consolidated Time Register 0 */

Definition at line 306 of file LPC21xx.h.

#define RTCCTIME1   RTC->ctime1 /* Consolidated Time Register 1 */

Definition at line 307 of file LPC21xx.h.

#define RTCCTIME2   RTC->ctime2 /* Consolidated Time Register 2 */

Definition at line 308 of file LPC21xx.h.

#define RTCDOM   RTC->dom /* Day Of Month Register */

Definition at line 312 of file LPC21xx.h.

#define RTCDOW   RTC->dow /* Day Of Week Register */

Definition at line 313 of file LPC21xx.h.

#define RTCDOY   RTC->doy /* Day Of Year Register */

Definition at line 314 of file LPC21xx.h.

#define RTCHOUR   RTC->hour /* Hours Register */

Definition at line 311 of file LPC21xx.h.

#define RTCILR   RTC->ilr /* Interrupt Location Register */

Definition at line 301 of file LPC21xx.h.

#define RTCMIN   RTC->min /* Minutes Register */

Definition at line 310 of file LPC21xx.h.

#define RTCMONTH   RTC->month /* Months Register */

Definition at line 315 of file LPC21xx.h.

#define RTCPREFRAC   RTC->prefrac /* Prescale Value Register (fraction) */

Definition at line 326 of file LPC21xx.h.

#define RTCPREINT   RTC->preint /* Prescale Value Register (integer) */

Definition at line 325 of file LPC21xx.h.

#define RTCSEC   RTC->sec /* Seconds Register */

Definition at line 309 of file LPC21xx.h.

#define RTCYEAR   RTC->year /* Years Register */

Definition at line 316 of file LPC21xx.h.

#define RTIC   1

Definition at line 291 of file LPC21xx.h.

Referenced by SpiClearRti().

#define RTIM   1

Definition at line 272 of file LPC21xx.h.

Referenced by SpiDisableRti(), and SpiEnableRti().

#define RTMIS   1

Definition at line 285 of file LPC21xx.h.

Referenced by SpiAutomaton(), and SpiSlaveAutomaton().

#define RXIM   2

Definition at line 273 of file LPC21xx.h.

Referenced by spi_slave_hs_init(), SpiDisableRxi(), and SpiEnableRxi().

#define RXMIS   2

Definition at line 286 of file LPC21xx.h.

#define S0SPCCR   SPI0->ccr /* Clock Counter Register */

Definition at line 201 of file LPC21xx.h.

#define S0SPCR   SPI0->cr /* Control Register */

Definition at line 198 of file LPC21xx.h.

#define S0SPDR   SPI0->dr /* Data Register */

Definition at line 200 of file LPC21xx.h.

#define S0SPINT   SPI0->flag /* Interrupt Flag Register */

Definition at line 202 of file LPC21xx.h.

#define S0SPSR   SPI0->sr /* Status Register */

Definition at line 199 of file LPC21xx.h.

#define SCB   ((scbRegs_t *)0xE01FC000)

Definition at line 394 of file LPC21xx.h.

Referenced by mcu_arch_init(), and mcu_deep_sleep().

#define SCR   8

Definition at line 247 of file LPC21xx.h.

#define SI   3

Definition at line 180 of file LPC21xx.h.

#define SIC   3

Definition at line 188 of file LPC21xx.h.

Referenced by I2cClearIT().

#define SOD   3

Definition at line 268 of file LPC21xx.h.

#define SPI0   ((spiRegs_t *)0xE0020000)

Definition at line 195 of file LPC21xx.h.

Referenced by spi0_arch_init().

#define SPI0IF   0

Definition at line 205 of file LPC21xx.h.

#define SPI1   ((sspRegs_t *)0xE0068000)

Definition at line 210 of file LPC21xx.h.

Referenced by spi1_arch_init().

#define SPI1IF   0

Definition at line 220 of file LPC21xx.h.

#define SSE   1

Definition at line 266 of file LPC21xx.h.

Referenced by spi_slave_hs_init(), and SpiDisable().

#define SSPCPSR   SPI1->cpsr /* Clock prescale register */
#define SSPCR0   SPI1->cr0 /* Control Register 0 */
#define SSPCR1   SPI1->cr1 /* Control Register 1 */
#define SSPDR   SPI1->dr /* Data register */
#define SSPICR   SPI1->icr /* Interrupt clear register */

Definition at line 230 of file LPC21xx.h.

#define SSPIMSC   SPI1->imsc /* Interrupt mask register */

Definition at line 227 of file LPC21xx.h.

Referenced by spi_slave_hs_init().

#define SSPMIS   SPI1->mis /* Masked interrupt status register */

Definition at line 229 of file LPC21xx.h.

#define SSPRIS   SPI1->ris /* Raw interrupt status register */

Definition at line 228 of file LPC21xx.h.

#define SSPSR   SPI1->sr /* Status register */

Definition at line 225 of file LPC21xx.h.

Referenced by SPI1_ISR().

#define STA   5

Definition at line 182 of file LPC21xx.h.

Referenced by I2cSendStart().

#define STAC   5

Definition at line 189 of file LPC21xx.h.

Referenced by I2cClearStart().

#define STO   4

Definition at line 181 of file LPC21xx.h.

Referenced by I2cFail(), and I2cSendStop().

#define T0CCR   TMR0->ccr /* Capture Control Register */
#define T0CR0   TMR0->cr0 /* Capture Register 0 */

Definition at line 61 of file LPC21xx.h.

#define T0CR1   TMR0->cr1 /* Capture Register 1 */

Definition at line 62 of file LPC21xx.h.

#define T0CR2   TMR0->cr2 /* Capture Register 2 */

Definition at line 63 of file LPC21xx.h.

#define T0CR3   TMR0->cr3 /* Capture Register 3 */

Definition at line 64 of file LPC21xx.h.

#define T0EMR   TMR0->emr /* External Match Register */
#define T0IR   TMR0->ir /* Interrupt Register */

Definition at line 50 of file LPC21xx.h.

Referenced by TIMER0_ISR().

#define T0MCR   TMR0->mcr /* Match Control Register */
#define T0MR0   TMR0->mr0 /* Match Register 0 */

Definition at line 56 of file LPC21xx.h.

Referenced by sys_tick_irq_handler(), and sys_time_arch_init().

#define T0MR1   TMR0->mr1 /* Match Register 1 */

Definition at line 57 of file LPC21xx.h.

Referenced by actuators_4015_init(), actuators_4017_init(), and actuators_ppm_init().

#define T0MR2   TMR0->mr2 /* Match Register 2 */

Definition at line 58 of file LPC21xx.h.

#define T0MR3   TMR0->mr3 /* Match Register 3 */

Definition at line 59 of file LPC21xx.h.

#define T0PC   TMR0->pc /* Prescale Counter Register */

Definition at line 54 of file LPC21xx.h.

#define T0PR   TMR0->pr /* Prescale Register */

Definition at line 53 of file LPC21xx.h.

Referenced by sys_time_arch_init().

#define T0TC   TMR0->tc /* Timer Counter */

Definition at line 52 of file LPC21xx.h.

Referenced by get_sys_time_msec(), get_sys_time_usec(), ms2100_reset_cb(), and sys_time_usleep().

#define T0TCR   TMR0->tcr /* Timer Control Register */

Definition at line 51 of file LPC21xx.h.

Referenced by sys_time_arch_init().

#define T1CCR   TMR1->ccr /* Capture Control Register */

Definition at line 82 of file LPC21xx.h.

#define T1CR0   TMR1->cr0 /* Capture Register 0 */

Definition at line 83 of file LPC21xx.h.

#define T1CR1   TMR1->cr1 /* Capture Register 1 */

Definition at line 84 of file LPC21xx.h.

#define T1CR2   TMR1->cr2 /* Capture Register 2 */

Definition at line 85 of file LPC21xx.h.

#define T1CR3   TMR1->cr3 /* Capture Register 3 */

Definition at line 86 of file LPC21xx.h.

#define T1EMR   TMR1->emr /* External Match Register */

Definition at line 87 of file LPC21xx.h.

#define T1IR   TMR1->ir /* Interrupt Register */

Definition at line 72 of file LPC21xx.h.

#define T1MCR   TMR1->mcr /* Match Control Register */

Definition at line 77 of file LPC21xx.h.

#define T1MR0   TMR1->mr0 /* Match Register 0 */

Definition at line 78 of file LPC21xx.h.

#define T1MR1   TMR1->mr1 /* Match Register 1 */

Definition at line 79 of file LPC21xx.h.

#define T1MR2   TMR1->mr2 /* Match Register 2 */

Definition at line 80 of file LPC21xx.h.

#define T1MR3   TMR1->mr3 /* Match Register 3 */

Definition at line 81 of file LPC21xx.h.

#define T1PC   TMR1->pc /* Prescale Counter Register */

Definition at line 76 of file LPC21xx.h.

#define T1PR   TMR1->pr /* Prescale Register */

Definition at line 75 of file LPC21xx.h.

#define T1TC   TMR1->tc /* Timer Counter */

Definition at line 74 of file LPC21xx.h.

#define T1TCR   TMR1->tcr /* Timer Control Register */

Definition at line 73 of file LPC21xx.h.

#define TFE   0

Definition at line 277 of file LPC21xx.h.

#define TMR0   ((pwmTmrRegs_t *)0xE0004000)

Definition at line 47 of file LPC21xx.h.

#define TMR1   ((pwmTmrRegs_t *)0xE0008000)

Definition at line 69 of file LPC21xx.h.

#define TNF   1

Definition at line 278 of file LPC21xx.h.

Referenced by SpiTransmit().

#define TXIM   3

Definition at line 274 of file LPC21xx.h.

Referenced by SpiDisableTxi(), and SpiEnableTxi().

#define TXMIS   3

Definition at line 287 of file LPC21xx.h.

Referenced by SpiAutomaton(), and SpiSlaveAutomaton().

#define U0_PINMASK   (0x0000000F) /* PINSEL0 Mask for UART0 */

Definition at line 114 of file LPC21xx.h.

#define U0_PINMASK_RX   (0x0000000C) /* PINSEL0 Mask for UART0 RX only */

Definition at line 116 of file LPC21xx.h.

#define U0_PINSEL   (0x00000005) /* PINSEL0 Value for UART0 */

Definition at line 113 of file LPC21xx.h.

#define U0_PINSEL_RX   (0x00000004) /* PINSEL0 Value for UART0 RX only */

Definition at line 115 of file LPC21xx.h.

#define U0DLL   UART0_BASE->dll /* Divisor Latch Register (LSB) */

Definition at line 127 of file LPC21xx.h.

#define U0DLM   UART0_BASE->dlm /* Divisor Latch Register (MSB) */

Definition at line 128 of file LPC21xx.h.

#define U0FCR   UART0_BASE->fcr /* FIFO Control Register */

Definition at line 123 of file LPC21xx.h.

#define U0IER   UART0_BASE->ier /* Interrupt Enable Register */

Definition at line 121 of file LPC21xx.h.

#define U0IIR   UART0_BASE->iir /* Interrupt ID Register */

Definition at line 122 of file LPC21xx.h.

#define U0LCR   UART0_BASE->lcr /* Line Control Register */

Definition at line 124 of file LPC21xx.h.

#define U0LSR   UART0_BASE->lsr /* Line Status Register */

Definition at line 125 of file LPC21xx.h.

#define U0RBR   UART0_BASE->rbr /* Receive Buffer Register */

Definition at line 119 of file LPC21xx.h.

#define U0SCR   UART0_BASE->scr /* Scratch Pad Register */

Definition at line 126 of file LPC21xx.h.

#define U0THR   UART0_BASE->thr /* Transmit Holding Register */

Definition at line 120 of file LPC21xx.h.

#define U1_PINMASK   (0x000F0000) /* PINSEL0 Mask for UART1 */

Definition at line 134 of file LPC21xx.h.

#define U1_PINMASK_RX   (0x000C0000) /* PINSEL0 Mask for UART1 RX only */

Definition at line 136 of file LPC21xx.h.

#define U1_PINSEL   (0x00050000) /* PINSEL0 Value for UART1 */

Definition at line 133 of file LPC21xx.h.

#define U1_PINSEL_RX   (0x00040000) /* PINSEL0 Value for UART1 RX only */

Definition at line 135 of file LPC21xx.h.

#define U1DLL   UART1_BASE->dll /* Divisor Latch Register (LSB) */

Definition at line 149 of file LPC21xx.h.

#define U1DLM   UART1_BASE->dlm /* Divisor Latch Register (MSB) */

Definition at line 150 of file LPC21xx.h.

#define U1FCR   UART1_BASE->fcr /* FIFO Control Register */

Definition at line 143 of file LPC21xx.h.

#define U1IER   UART1_BASE->ier /* Interrupt Enable Register */

Definition at line 141 of file LPC21xx.h.

#define U1IIR   UART1_BASE->iir /* Interrupt ID Register */

Definition at line 142 of file LPC21xx.h.

#define U1LCR   UART1_BASE->lcr /* Line Control Register */

Definition at line 144 of file LPC21xx.h.

#define U1LSR   UART1_BASE->lsr /* Line Status Register */

Definition at line 146 of file LPC21xx.h.

#define U1MCR   UART1_BASE->mcr /* MODEM Control Register */

Definition at line 145 of file LPC21xx.h.

#define U1MSR   UART1_BASE->msr /* MODEM Status Register */

Definition at line 147 of file LPC21xx.h.

#define U1RBR   UART1_BASE->rbr /* Receive Buffer Register */

Definition at line 139 of file LPC21xx.h.

#define U1SCR   UART1_BASE->scr /* Scratch Pad Register */

Definition at line 148 of file LPC21xx.h.

#define U1THR   UART1_BASE->thr /* Transmit Holding Register */

Definition at line 140 of file LPC21xx.h.

#define UART0_BASE   ((uartRegs_t *)0xE000C000)

Definition at line 112 of file LPC21xx.h.

#define UART1_BASE   ((uartRegs_t *)0xE0010000)

Definition at line 132 of file LPC21xx.h.

#define VIC   ((vicRegs_t *)0xFFFFF000)

Definition at line 424 of file LPC21xx.h.

#define VICDefVectAddr   VIC->defVectAddr /* Default Vector Address Register */

Definition at line 437 of file LPC21xx.h.

Referenced by mcu_arch_init().

#define VICFIQStatus   VIC->fiqStatus /* FIQ Status Register */

Definition at line 428 of file LPC21xx.h.

#define VICIntEnClear   VIC->intEnClear /* Interrupt Enable Clear Register */

Definition at line 432 of file LPC21xx.h.

Referenced by mcu_arch_init(), spi_lock(), and spi_resume().

#define VICIRQStatus   VIC->irqStatus /* IRQ Status Register */

Definition at line 427 of file LPC21xx.h.

#define VICProtection   VIC->protection /* Protection Enable Register */

Definition at line 435 of file LPC21xx.h.

#define VICRawIntr   VIC->rawIntr /* Raw Interrupt Status Register */

Definition at line 429 of file LPC21xx.h.

#define VICSoftInt   VIC->softInt /* Software Interrupt Register */

Definition at line 433 of file LPC21xx.h.

#define VICSoftIntClear   VIC->softIntClear /* Software Interrupt Clear Register */

Definition at line 434 of file LPC21xx.h.

#define VICVectAddr   VIC->vectAddr /* Vector Address Register */
#define VICVectAddr0   VIC->vectAddr0 /* Vector Address 0 Register */

Definition at line 438 of file LPC21xx.h.

#define VICVectAddr1   VIC->vectAddr1 /* Vector Address 1 Register */

Definition at line 439 of file LPC21xx.h.

#define VICVectAddr10   VIC->vectAddr10 /* Vector Address 10 Register */

Definition at line 448 of file LPC21xx.h.

#define VICVectAddr11   VIC->vectAddr11 /* Vector Address 11 Register */

Definition at line 449 of file LPC21xx.h.

Referenced by baro_scp_init().

#define VICVectAddr12   VIC->vectAddr12 /* Vector Address 12 Register */

Definition at line 450 of file LPC21xx.h.

#define VICVectAddr13   VIC->vectAddr13 /* Vector Address 13 Register */

Definition at line 451 of file LPC21xx.h.

#define VICVectAddr14   VIC->vectAddr14 /* Vector Address 14 Register */

Definition at line 452 of file LPC21xx.h.

#define VICVectAddr15   VIC->vectAddr15 /* Vector Address 15 Register */

Definition at line 453 of file LPC21xx.h.

#define VICVectAddr2   VIC->vectAddr2 /* Vector Address 2 Register */

Definition at line 440 of file LPC21xx.h.

#define VICVectAddr3   VIC->vectAddr3 /* Vector Address 3 Register */

Definition at line 441 of file LPC21xx.h.

#define VICVectAddr4   VIC->vectAddr4 /* Vector Address 4 Register */

Definition at line 442 of file LPC21xx.h.

#define VICVectAddr5   VIC->vectAddr5 /* Vector Address 5 Register */

Definition at line 443 of file LPC21xx.h.

#define VICVectAddr6   VIC->vectAddr6 /* Vector Address 6 Register */

Definition at line 444 of file LPC21xx.h.

#define VICVectAddr7   VIC->vectAddr7 /* Vector Address 7 Register */

Definition at line 445 of file LPC21xx.h.

#define VICVectAddr8   VIC->vectAddr8 /* Vector Address 8 Register */

Definition at line 446 of file LPC21xx.h.

#define VICVectAddr9   VIC->vectAddr9 /* Vector Address 9 Register */

Definition at line 447 of file LPC21xx.h.

#define VICVectCntl0   VIC->vectCntl0 /* Vector Control 0 Register */

Definition at line 454 of file LPC21xx.h.

#define VICVectCntl1   VIC->vectCntl1 /* Vector Control 1 Register */

Definition at line 455 of file LPC21xx.h.

#define VICVectCntl10   VIC->vectCntl10 /* Vector Control 10 Register */

Definition at line 464 of file LPC21xx.h.

#define VICVectCntl11   VIC->vectCntl11 /* Vector Control 11 Register */

Definition at line 465 of file LPC21xx.h.

Referenced by baro_scp_init().

#define VICVectCntl12   VIC->vectCntl12 /* Vector Control 12 Register */

Definition at line 466 of file LPC21xx.h.

#define VICVectCntl13   VIC->vectCntl13 /* Vector Control 13 Register */

Definition at line 467 of file LPC21xx.h.

#define VICVectCntl14   VIC->vectCntl14 /* Vector Control 14 Register */

Definition at line 468 of file LPC21xx.h.

#define VICVectCntl15   VIC->vectCntl15 /* Vector Control 15 Register */

Definition at line 469 of file LPC21xx.h.

#define VICVectCntl2   VIC->vectCntl2 /* Vector Control 2 Register */

Definition at line 456 of file LPC21xx.h.

#define VICVectCntl3   VIC->vectCntl3 /* Vector Control 3 Register */

Definition at line 457 of file LPC21xx.h.

#define VICVectCntl4   VIC->vectCntl4 /* Vector Control 4 Register */

Definition at line 458 of file LPC21xx.h.

#define VICVectCntl5   VIC->vectCntl5 /* Vector Control 5 Register */

Definition at line 459 of file LPC21xx.h.

#define VICVectCntl6   VIC->vectCntl6 /* Vector Control 6 Register */

Definition at line 460 of file LPC21xx.h.

#define VICVectCntl7   VIC->vectCntl7 /* Vector Control 7 Register */

Definition at line 461 of file LPC21xx.h.

#define VICVectCntl8   VIC->vectCntl8 /* Vector Control 8 Register */

Definition at line 462 of file LPC21xx.h.

#define VICVectCntl9   VIC->vectCntl9 /* Vector Control 9 Register */

Definition at line 463 of file LPC21xx.h.

#define VPBDIV   SCB->vpbdiv

Definition at line 414 of file LPC21xx.h.

Referenced by mcu_arch_init().

#define WD   ((wdRegs_t *)0xE0000000)

Definition at line 37 of file LPC21xx.h.

#define WDFEED   WD->feed /* Watchdog Feed Register */

Definition at line 42 of file LPC21xx.h.

#define WDMOD   WD->mod /* Watchdog Mode Register */

Definition at line 40 of file LPC21xx.h.

#define WDTC   WD->tc /* Watchdog Time Constant Register */

Definition at line 41 of file LPC21xx.h.

#define WDTV   WD->tv /* Watchdog Time Value Register */

Definition at line 43 of file LPC21xx.h.